Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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5.1.8. HPS Shared I/O Requirements

The HPS EMIF uses I/O pins located in the GPIO bank instead of HPS I/O bank. The 1.2 V VCCIO_PIO powers the GPIO bank instead of the 1.8 V VCCIO_HPS. Refer to the Intel® Agilex™ device pin-out for the location of the HPS shared GPIO pins.

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