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1. Intel® Agilex™ General-Purpose I/O and LVDS SERDES Overview
2. Intel® Agilex™ I/O Features and Usage
3. Intel® Agilex™ I/O Termination
4. Intel® Agilex™ High-Speed SERDES I/O Architecture
5. I/O and LVDS SERDES Design Guidelines
6. Troubleshooting Guidelines
7. Documentation Related to the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide
8. Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide Archives
9. Document Revision History for the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide
2.2.1. Programmable Output Slew Rate Control
2.2.2. Programmable IOE Delay
2.2.3. Programmable Open-Drain Output
2.2.4. Programmable Bus-Hold
2.2.5. Programmable Pull-Up Resistor
2.2.6. Programmable Pre-emphasis
2.2.7. Programmable De-emphasis
2.2.8. Programmable Differential Output Voltage
2.2.9. Schmitt Trigger Input Buffer
4.1. Intel® Agilex™ High-Speed SERDES I/O Overview
4.2. Using LVDS SERDES Intel FPGA IP for High-Speed LVDS I/O Implementation
4.3. Intel® Agilex™ LVDS SERDES Transmitter
4.4. Intel® Agilex™ LVDS SERDES Receiver
4.5. Intel® Agilex™ LVDS Interface with External PLL Mode
4.6. LVDS SERDES IP Initialization and Reset
4.7. Intel® Agilex™ LVDS SERDES Source-Synchronous Timing Budget
4.8. LVDS SERDES IP Timing
4.9. LVDS SERDES IP Design Examples
5.1.1. VREF Sources and VREF Pins
5.1.2. I/O Standards Implementation based on VCCIO_PIO Voltages
5.1.3. OCT Calibration Block Requirement
5.1.4. Placement Requirements
5.1.5. Simultaneous Switching Noise (SSN)
5.1.6. Special Pins Requirement
5.1.7. External Memory Interface Pin Placement Requirements
5.1.8. HPS Shared I/O Requirements
5.1.9. Clocking Requirements
5.1.10. SDM Shared I/O Requirements
5.1.11. Configuration Pins
5.1.12. Unused Pins
5.1.13. Voltage Setting for Unused I/O Banks
5.1.14. Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing
5.1.15. Drive Strength Requirement for GPIO Input Pins
5.1.16. Maximum DC Current Restrictions
5.1.17. 1.2 V I/O Interface Voltage Level Compatibility
5.1.18. GPIO Pins for Avalon-ST Configuration Scheme
5.1.19. Maximum True Differential Signaling RX Pairs Per I/O Lane
5.1.20. I/O Simulation
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2.4.2.5.1. Timing Components
The GPIO IP core timing components consist of three paths.
- I/O interface paths—from the FPGA to external receiving devices and from external transmitting devices to the FPGA.
- Core interface paths of data and clock—from the I/O to the core and from the core to I/O.
- Transfer paths—from half-rate to full-rate DDIO, and from full-rate to half-rate DDIO.
Note: The Timing Analyzer treats the path inside the DDIO_IN and DDIO_OUT blocks as black boxes.
Figure 24. Input Path Timing Components
Figure 25. Output Path Timing Components
Figure 26. Output Enable Path Timing Components
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