Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

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Document Table of Contents Timing Components

The GPIO IP core timing components consist of three paths.
  • I/O interface paths—from the FPGA to external receiving devices and from external transmitting devices to the FPGA.
  • Core interface paths of data and clock—from the I/O to the core and from the core to I/O.
  • Transfer paths—from half-rate to full-rate DDIO, and from full-rate to half-rate DDIO.
Note: The Timing Analyzer treats the path inside the DDIO_IN and DDIO_OUT blocks as black boxes.
Figure 24. Input Path Timing Components

Figure 25. Output Path Timing Components

Figure 26. Output Enable Path Timing Components

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