Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.4.2.5.1. Timing Components

The GPIO IP core timing components consist of three paths.
  • I/O interface paths—from the FPGA to external receiving devices and from external transmitting devices to the FPGA.
  • Core interface paths of data and clock—from the I/O to the core and from the core to I/O.
  • Transfer paths—from half-rate to full-rate DDIO, and from full-rate to half-rate DDIO.
Note: The Timing Analyzer treats the path inside the DDIO_IN and DDIO_OUT blocks as black boxes.
Figure 24. Input Path Timing Components


Figure 25. Output Path Timing Components


Figure 26. Output Enable Path Timing Components


Did you find the information on this page useful?

Characters remaining:

Feedback Message