Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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5.1.17. 1.2 V I/O Interface Voltage Level Compatibility

Evaluate the electrical signal level compatibility between Intel® Agilex™ 1.2 V output and the downstream device to ensure the 1.2 V output buffer Voh and Vol voltages are within the downstream's receiving buffer's Vih and Vil specifications.
The following examples showcase Intel® Agilex™ 1.2 V output voltage swing calculations:
  • Example 1:
    • When using 1.2 V LVCMOS, the output signal swings from 0 V to 1.2 V on a lossless transmission line with no external pull-up or pull-down component. You must ensure the VIH or VIL tolerance of the downstream connecting device is able to meet those conditions.
  • Example 2:
    • When using 1.2V voltage referenced I/O standards, the output signal swing has a dependency on the external board termination or the receiver’s internal termination. The following diagram shows an example termination setup and its equivalent circuit.
Figure 89. Termination Setup using 40 Ω RS OCT Driver with On-Board 50 Ω Pull-Up Resistor to VCCIO_PIO/2

When the output buffer is driving HIGH, the pin voltage is 0.93 V based on voltage divider rule.

Figure 90. Equivalent Circuit of Example 2 with Output Buffer Driving HIGH

When the output buffer is driving LOW, the pin voltage is 0.27 V based on voltage divider rule.

Figure 91. Equivalent Circuit of Example 2 with Output Buffer Driving LOW

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