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1. Intel® Agilex™ General-Purpose I/O and LVDS SERDES Overview
2. Intel® Agilex™ I/O Features and Usage
3. Intel® Agilex™ I/O Termination
4. Intel® Agilex™ High-Speed SERDES I/O Architecture
5. I/O and LVDS SERDES Design Guidelines
6. Troubleshooting Guidelines
7. Documentation Related to the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide
8. Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide Archives
9. Document Revision History for the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide
2.2.1. Programmable Output Slew Rate Control
2.2.2. Programmable IOE Delay
2.2.3. Programmable Open-Drain Output
2.2.4. Programmable Bus-Hold
2.2.5. Programmable Pull-Up Resistor
2.2.6. Programmable Pre-emphasis
2.2.7. Programmable De-emphasis
2.2.8. Programmable Differential Output Voltage
2.2.9. Schmitt Trigger Input Buffer
4.1. Intel® Agilex™ High-Speed SERDES I/O Overview
4.2. Using LVDS SERDES Intel FPGA IP for High-Speed LVDS I/O Implementation
4.3. Intel® Agilex™ LVDS SERDES Transmitter
4.4. Intel® Agilex™ LVDS SERDES Receiver
4.5. Intel® Agilex™ LVDS Interface with External PLL Mode
4.6. LVDS SERDES IP Initialization and Reset
4.7. Intel® Agilex™ LVDS SERDES Source-Synchronous Timing Budget
4.8. LVDS SERDES IP Timing
4.9. LVDS SERDES IP Design Examples
5.1.1. VREF Sources and VREF Pins
5.1.2. I/O Standards Implementation based on VCCIO_PIO Voltages
5.1.3. OCT Calibration Block Requirement
5.1.4. Placement Requirements
5.1.5. Simultaneous Switching Noise (SSN)
5.1.6. Special Pins Requirement
5.1.7. External Memory Interface Pin Placement Requirements
5.1.8. HPS Shared I/O Requirements
5.1.9. Clocking Requirements
5.1.10. SDM Shared I/O Requirements
5.1.11. Configuration Pins
5.1.12. Unused Pins
5.1.13. Voltage Setting for Unused I/O Banks
5.1.14. Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing
5.1.15. Drive Strength Requirement for GPIO Input Pins
5.1.16. Maximum DC Current Restrictions
5.1.17. 1.2 V I/O Interface Voltage Level Compatibility
5.1.18. GPIO Pins for Avalon-ST Configuration Scheme
5.1.19. Maximum True Differential Signaling RX Pairs Per I/O Lane
5.1.20. I/O Simulation
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5.1.17. 1.2 V I/O Interface Voltage Level Compatibility
Evaluate the electrical signal level compatibility between Intel® Agilex™ 1.2 V output and the downstream device to ensure the 1.2 V output buffer Voh and Vol voltages are within the downstream's receiving buffer's Vih and Vil specifications.
The following examples showcase Intel® Agilex™ 1.2 V output voltage swing calculations:
- Example 1:
- When using 1.2 V LVCMOS, the output signal swings from 0 V to 1.2 V on a lossless transmission line with no external pull-up or pull-down component. You must ensure the VIH or VIL tolerance of the downstream connecting device is able to meet those conditions.
- Example 2:
- When using 1.2V voltage referenced I/O standards, the output signal swing has a dependency on the external board termination or the receiver’s internal termination. The following diagram shows an example termination setup and its equivalent circuit.
Figure 89. Termination Setup using 40 Ω RS OCT Driver with On-Board 50 Ω Pull-Up Resistor to VCCIO_PIO/2
When the output buffer is driving HIGH, the pin voltage is 0.93 V based on voltage divider rule.
Figure 90. Equivalent Circuit of Example 2 with Output Buffer Driving HIGH
When the output buffer is driving LOW, the pin voltage is 0.27 V based on voltage divider rule.
Figure 91. Equivalent Circuit of Example 2 with Output Buffer Driving LOW