Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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4.2.2.2.5. LVDS SERDES IP Clock Resource Summary

The Clock Resource Summary tab lists the required frequencies, phase shifts, duty cycles of the required clocks, instructions for connections, and compensation mode that you need to set in the IOPLL Intel® FPGA IP.
The following table shows the description for each configuration listed in the Clock Resource Summary tab.
Table 60.  Clock Resource Summary Configuration Description
Configuration Description
PLL VCO Specifies the frequency that you need to set to the Desired VCO Frequency parameter in the IOPLL IP.
Fast clock Specifies the frequency, phase shift, duty cycle that you need to set for lvds_clk[1:0] ports in the IOPLL IP.
Load enable Specifies the frequency, phase shift, duty cycle that you need to set for loaden[1:0] ports in the IOPLL IP.
Core clock Specifies the frequency, phase shift, duty cycle that you need to set for any PLL output clock from the IOPLL IP that is used for core clock connection.
Compensation Mode Specifies the option you should select for the Compensation Mode parameter in the IOPLL IP.

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