Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.1.1. Receiver Blocks in Intel® Agilex™ Devices

The Intel® Agilex™ LVDS SERDES receiver has the following hardware blocks:

  • DPA block
  • Synchronizer
  • Data realignment block (bit slip)
  • Deserializer
Figure 61. Receiver Block DiagramThis figure shows the hardware blocks of the receiver. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively. The deserializer includes shift registers and parallel load registers, and sends a maximum of 10 bits to the internal logic.

Did you find the information on this page useful?

Characters remaining:

Feedback Message