Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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1.3. I/O Banks

There are three types of I/O banks available in the Intel® Agilex™ I/O interface system.
  • GPIO banks
  • HPS I/O bank
  • SDM I/O bank

In each GPIO bank, there are two sub-banks. The top sub-bank is placed near the edge of the die, and the bottom sub-bank is placed near the FPGA core. The top sub-bank pin indexes are 48-95 and the bottom sub-bank pin indexes are 0-47.

In each sub-bank, there are four I/O lanes with 12 I/O pins in each lane that make up a total of 48 single-ended I/O pins or 24 true differential I/O pairs per sub-bank. When SERDES is used, each I/O lane supports three dedicated differential receiver input buffer pairs and three dedicated differential transmitter output buffer pairs, with SERDES and dynamic phase alignment (DPA) channels. When SERDES is not used, you can configure the true differential buffers as receivers or transmitters with the maximum of three receiver pairs within an I/O lane.

Other than the I/O lanes, SERDES, and DPA, each I/O sub-bank also contains dedicated circuitries including I/O PLL, hard memory controller, and on-chip termination (OCT) calibration blocks.

The total bank count in a GPIO bank varies across different device packages. Certain GPIO banks are shared with the SDM and HPS function blocks. Refer to the device pin-out files for available GPIO banks, GPIO and SDM shared I/O banks, and GPIO and HPS shared I/O banks per package.

The HPS I/O bank consists of 48 I/O pins. These pins are used for HPS clocks, peripherals, mass storage flash, and JTAG.

The SDM I/O bank consists of 24 dedicated pins for device configuration purposes. Refer to the device pin-out files for the dedicated function of each pin in the SDM I/O bank.

Figure 2.  Intel® Agilex™ I/O Bank Structure (Top View)This diagram shows the I/O bank structure of the Intel® Agilex™ AGI 027 device. Different device packages have different number of I/O banks. Refer to the device pin-out files for available I/O banks for each device package.

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