Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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The Intel® Quartus® Prime software does not automatically generate the SDC timing constraints for the GPIO IP core. You must manually enter the timing constraints.

Follow the timing guidelines and examples to ensure that the Timing Analyzer analyzes the I/O timing correctly.

  • To perform proper timing analysis for the I/O interface paths, specify the system level constraints of the data pins against the system clock pin in the .sdc file.
  • To perform proper timing analysis for the core interface paths, define these clock settings in the .sdc file:
    • Clock to the core registers
    • Clock to the I/O registers for the simple register and DDIO modes

Single Data Rate Input Register

Figure 27. Single Data Rate Input Register


Table 32.  Single Data Rate Input Register .sdc Command Examples
Command Command Example Description
create_clock create_clock -name sdr_in_clk -period "100 MHz" sdr_in_clk Creates clock setting for the input clock.
set_input_delay set_input_delay -clock sdr_in_clk 0.15 sdr_in_data Instructs the Timing Analyzer to analyze the timing of the input I/O with a 0.15 ns input delay.

Full-Rate or Half-Rate DDIO Input Register

The input side of the full-rate and half-rate DDIO input registers are the same. You can properly constrain the system by using a virtual clock to model the off-chip transmitter to the FPGA.
Figure 28. Full-Rate or Half-Rate DDIO Input Register


Table 33.  Full-Rate or Half-Rate DDIO Input Register .sdc Command Examples
Command Command Example Description
create_clock

create_clock -name virtual_clock -period "200 MHz"

create_clock -name ddio_in_clk -period "200 MHz" ddio_in_clk

Create clock setting for the virtual clock and the DDIO clock.
set_input_delay

set_input_delay -clock virtual_clock 0.25 ddio_in_data

set_input_delay -add_delay -clock_fall -clock virtual_clock 0.25 ddio_in_data

Instruct the Timing Analyzer to analyze the positive clock edge and the negative clock edge of the transfer. Note the -add_delay in the second set_input_delay command.
set_false_path

set_false_path -fall_from virtual_clock -rise_to ddio_in_clk

set_false_path -rise_from virtual_clock -fall_to ddio_in_clk

Instruct the Timing Analyzer to ignore the positive clock edge to the negative edge triggered register, and the negative clock edge to the positive edge triggered register.

Note: The ck_hr frequency must be half the ck_fr frequency. If the I/O PLL drives the clocks, you can consider using the derive_pll_clocks .sdc command.

Single Data Rate Output Register

Figure 29.  Single Data Rate Output Register


Table 34.  Single Data Rate Output Register .sdc Command Examples
Command Command Example Description
create_clock and create_generated_clock

create_clock -name sdr_out_clk -period "100 MHz" sdr_out_clk

create_generated_clock -source sdr_out_clk -name sdr_out_outclk sdr_out_outclk

Generate the source clock and the output clock to transmit.
set_output_delay set_output_delay -clock sdr_out_clk 0.45 sdr_out_data Instructs the Timing Analyzer to analyze the output data to transmit against the output clock to transmit.

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