Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

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Document Table of Contents Net Length Reports

The net length information consists of the package trace delay information from die pad to package pin. Each pin in an FPGA package has its own net length information. This information is important for you to perform board trace compensation to optimize the channel-to-channel skew on your board design.

You can obtain the net length reports for Intel® Agilex™ devices from the Board Design Guidelines Solutions Center under Tools, Models, and Libraries.

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