Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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4.5.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode

Figure 73. Non-DPA or DPA LVDS Receiver Interface with the IOPLL IP (without LVDS transmitter in the same sub-bank)
Figure 74. Non-DPA or DPA LVDS Receiver Interface with the IOPLL IP (with LVDS transmitter in the same sub-bank)
Figure 75. Soft-CDR LVDS Receiver Interface with the IOPLL IP (without LVDS transmitter in the same sub-bank)
Figure 76. Soft-CDR LVDS Receiver Interface with the IOPLL IP (with LVDS transmitter in the same sub-bank)
Figure 77. LVDS Transmitter Interface with the IOPLL IP

The ext_coreclock port is automatically enabled in the LVDS SERDES IP in external PLL mode. The Intel® Quartus® Prime compiler outputs error messages if this port is not connected as shown in the preceding figures.

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