Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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4.4.3.1. Non-DPA Mode

The non-DPA mode disables the DPA and synchronizer blocks. Input serial data is registered at the rising edge of the serial fast_clock clock that is produced by the I/O PLLs.

The fast_clock clock that is generated by the I/O PLLs clocks the data realignment and deserializer blocks.

Figure 69. Receiver Datapath in Non-DPA ModeThis figure shows the non-DPA datapath block diagram.

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