Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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5.1.19. Maximum True Differential Signaling RX Pairs Per I/O Lane

You can configure any of the true differential I/O buffers to a maximum of three true differential signaling receiver pairs per each I/O lane when SERDES is not used. You can place the true differential signaling RX pairs anywhere within the same I/O lane. The following figure shows the examples of three true differential signaling RX pairs placement within an I/O lane.

Figure 92. Examples of True Differential Signaling RX Pairs Placement

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