Intel® Agilex™ F-Series and I-Series Power Management User Guide

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ID 683373
Date 12/19/2022
Public
Document Table of Contents
Document Table of Contents
1. Intel® Agilex™ F-Series and I-Series Power Management Overview 2. Intel® Agilex™ Power Basics 3. Intel® Agilex™ Power and I/O State Sequencing 4. Intel® Agilex™ F-Series and I-Series Sensor Monitoring System 5. Intel® Agilex™ Power Optimization Techniques and Features 6. Document Revision History for the Intel® Agilex™ Power Management User Guide
1. Intel® Agilex™ F-Series and I-Series Power Management Overview
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Intel® Agilex™ Power Basics
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Intel® FPGA Power and Thermal Calculator 2.4. Power Analyzer
3. Intel® Agilex™ Power and I/O State Sequencing
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Power-Down Sequence Requirements for Intel® Agilex™ Devices with E-Tile 3.4. Floating Voltage 3.5. Power-On Reset
3.2. Power-Up Sequence Requirements
3.2.1. Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing
3.5. Power-On Reset
3.5.1. Power Supplies Monitored by the POR Circuitry
4. Intel® Agilex™ F-Series and I-Series Sensor Monitoring System
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Intel® Agilex™ Sensors Design Considerations 4.4. Temperature Reading Design Example
4.1. Voltage Monitoring System
4.1.1. Voltage Sensor Transfer Function
4.2. Temperature Monitoring System
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.3. Intel® Agilex™ Sensors Design Considerations
4.3.1. Intel® Agilex™ Voltage Monitor Design Guidelines 4.3.2. Intel® Agilex™ Temperature Monitor Design Guidelines 4.3.3. Intel® Agilex™ Transceiver Tile Local Temperature Sensor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Intel® Agilex™ Remote TSD
4.4. Temperature Reading Design Example
4.4.1. Directory Structure 4.4.2. Hardware and Software Requirements 4.4.3. Temperature Reading Design Example Description 4.4.4. Using the Temperature Reading Design Example 4.4.5. Verifying the Interaction between the Design Example and the Mailbox Client with Avalon® Streaming Interface IP
4.4.4. Using the Temperature Reading Design Example
4.4.4.1. Opening the Temperature Reading Design Example 4.4.4.2. Compiling the Temperature Reading Design Example and Generating the Software Object File 4.4.4.3. Programming and Starting Up the Temperature Reading Design Example 4.4.4.4. Sending Commands to the Temperature Reading Design Example
4.4.4.4. Sending Commands to the Temperature Reading Design Example
4.4.4.4.1. Default Commands for the Temperature Reading Design Example
5. Intel® Agilex™ Power Optimization Techniques and Features
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Intel® Quartus® Prime Software
5.1. SmartVID Standard Power Devices
5.1.1. SmartVID Feature Implementation in Intel® Agilex™ Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Intel® Agilex™ Power Management and VID Implementation Guide
5.1.2. SDM Power Manager
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Intel® Agilex™ Power Management and VID Implementation Guide
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Intel® Agilex™ Power Management and VID Interface QSF Constraint Guide
1. Intel® Agilex™ F-Series and I-Series Power Management Overview
2. Intel® Agilex™ Power Basics
3. Intel® Agilex™ Power and I/O State Sequencing
4. Intel® Agilex™ F-Series and I-Series Sensor Monitoring System
5. Intel® Agilex™ Power Optimization Techniques and Features
6. Document Revision History for the Intel® Agilex™ Power Management User Guide

3.5. Power-On Reset

The power-on reset (POR) circuitry keeps the Intel® Agilex™ device in the reset state until the power supply outputs are within the recommended operating range.

A POR event occurs when you power up the Intel® Agilex™ device until all power supplies monitored by the POR circuitry reach the recommended operating range within the maximum power supply ramp time, tRAMP . If tRAMP is not met, the Intel® Agilex™ device I/O pins and programming registers remain tri-stated, which may cause device configuration to fail.

Figure 4. Relationship Between tRAMP and POR DelayThe boot ROM initialization sequence is part of the POR delay. For tRAMP and POR delay specifications, refer to the Intel® Agilex™ Device Data Sheet.

The Intel® Agilex™ POR circuitry uses individual detection circuitry to monitor each of the configuration-related power supplies independently. The POR circuitry is gated by the outputs of all the individual detectors.

POR delay is the time from when the POR trips out to the final reset signal. For POR trip level, you can use the minimum value of the last power supply as a reference.

The Intel® Agilex™ device is held in the POR state until all power supplies have passed their trigger point. After power supplies have passed the trigger point, the Secure Device Manager (SDM) waits for a configurable delay time and then starts device configuration.


Section Content
Power Supplies Monitored by the POR Circuitry

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