Intel Agilex® 7 Power Management User Guide

ID 683373
Date 12/04/2023
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3.5. Power-On Reset

The power-on reset (POR) circuitry keeps the Intel Agilex® 7 device in the reset state until the power supply outputs are within the recommended operating range.

A POR event occurs when you power up the Intel Agilex® 7 device until all power supplies monitored by the POR circuitry reach the recommended operating range within the maximum power supply ramp time, tRAMP . If tRAMP is not met, the Intel Agilex® 7 device I/O pins remain tri-stated, and programming registers remain reset, which may cause device configuration to fail.

Figure 5. Relationship Between tRAMP and POR DelayThe boot ROM initialization sequence is part of the POR delay. For tRAMP and POR delay specifications, refer to the Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series .

The Intel Agilex® 7 POR circuitry uses individual detection circuitry to monitor each of the configuration-related power supplies independently. The POR circuitry is gated by the outputs of all the individual detectors.

POR delay is the time from when the POR trips out to the final reset signal. For POR trip level, you can use the minimum value of the last power supply as a reference.

The Intel Agilex® 7 device is held in the POR state until all power supplies have passed their trigger point. After power supplies have passed the trigger point, the Secure Device Manager (SDM) waits for a configurable delay time and then starts device configuration.