Intel® Agilex™ Power Management User Guide

ID 683373
Date 9/06/2022
Public
Document Table of Contents

3.1. Overview

The Intel® Agilex™ devices require a specific power sequence.

This section describes several power management options and discusses proper I/O management during device power up and power down. Design your power supply solution to properly control the complete power sequence. The requirements in this section must be followed to prevent unpredictable current draw to the FPGA device, which can potentially impact the I/O functionality.

Table 2.  Power Rails Status for Intel® Agilex™ Devices
Tile Status
E-Tile Final
P-Tile Final
F-Tile Preliminary
R-Tile Preliminary

The following descriptors designate the status level currently applicable to the relevant variant:

  • Preliminary: Information in this document is subject to change. Intended for pre-production development, for production designs use with caution.
  • Final: Information in this document is intended for use in production design.

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