5.1. SmartVID Standard Power Devices
This feature is supported in all Intel Agilex® 7 devices with the –V, –E, and –X power options only. For the –V, –E, and –X power option devices, you must connect the PWRMGT_SCL and PWRMGT_SDA pins in both the Power Management BUS (PMBus™) master and PMBus slave modes. The PWRMGT_ALERT pin is required for the Intel Agilex® 7 device in the PMBus slave mode. The PWRMGT_ALERT pin is an active low pin and is used to perform the handshake flow between the FPGA device and an external PMBus master. All connections must be set up on the circuit board and in the Intel® Quartus® Prime software.
|PMBus Interfaces||Operating Modes|
|PMBus Master Mode||PMBus Slave Mode|
The PMBus master and PMBus slave modes only support the 1.8-V single-ended I/O standard.
For more information about how to connect these pins on the circuit board, refer to the Intel Agilex® 7 Device Family Pin Connection Guidelines: F-Series and I-Series .
For instructions on how to set up the connections in the Intel® Quartus® Prime software, refer to the Specifying Power Management and VID Parameters and Options.
Intel® programs the optimum voltage level required by each individual FPGA device into a fuse block during device manufacturing. The Secure Device Manager (SDM) Power Manager reads these values and can communicate them to an external power regulator or a system power controller through the PMBus interface.
The SmartVID feature allows a power regulator to provide the Intel Agilex® 7 devices with VCC and VCCP voltage levels that maintain the performance of the specific device speed grade. When the SmartVID feature is used:
- Intel Agilex® 7 devices are powered up at 0.80V regardless of speed grade for both VCC and VCCP .
- After the VID-fused value in the FPGA is determined and propagated to the external voltage regulator, both the VCC and VCCP voltages are regulated based on the boosted VID-fused value.