Intel Agilex® 7 Power Management User Guide

ID 683373
Date 10/31/2023
Document Table of Contents Fail Safe Mechanism

If a miscommunication situation happens between the FPGA device and the external voltage regulator, the voltage regulator might be supplying unexpected voltage to the FPGA device.

To avoid voltage supply issue to the FPGA device, a safety net check processing is implemented in the Intel® Quartus® Prime software against your input setting (coefficient value—m, b, r for the direct mode and N for the linear mode) in the power management GUI.

The fail safe mechanism detects the early issue during the configuration phase, before the PMBus communication is established with the voltage regulator, prior to any voltage adjustment. If an error occurred, configuration is unsuccessful.

The Intel® Quartus® Prime software maintains a list of Intel® validated voltage regulator's coefficient values. During configuration, the firmware performs the calculation and conversion based on the information of your selected voltage regulator in the Intel® Quartus® Prime GUI to obtain the respective voltage regulator data, using the PMBus Direct or Linear format formula. The calculated data is then compared against the Intel® 's maintained voltage regulator information in the Intel® Quartus® Prime software. If there is no matching data, configuration fails and the VOUT_COMMAND is not sent. However, this safety net check is not applicable when you select the voltage regulator type as "Other" in the Intel® Quartus® Prime GUI.