Intel® Agilex™ Power Management User Guide

ID 683373
Date 9/06/2022
Public
Document Table of Contents

4.4.3. Temperature Reading Design Example Description

The Temperature Reading design example exposes a JTAG-to- Avalon® streaming interface that allows you to interact with the design example modules through the Intel® Quartus® Prime System Console.
Figure 13. Temperature Reading Design Example Block Diagram


All the Intel® Quartus® Prime System Console read and write commands control a set of parallel I/O IPs that select a command for the Mailbox Client with Avalon® Streaming Interface IP to execute. At the same time, the parallel I/O IPs control a FIFO IP that stores all the Mailbox Client with Avalon® Streaming Interface IP responses.

Table 11.  Description of Modules in the Design Example
Module Description
u_avst_fsm_cmd

This module connects to a four-bit wide bus that selects a command for a finite state machine to send to the Mailbox Client with Avalon® Streaming Interface IP. The available commands are hardcoded in a look-up table (LUT) modeled in the command_rom.sv file. You can modify the LUT to edit existing commands or include new commands.

Command LUT ROM bit order:

  • [37..34]—the command ROM address that contains the next argument of the command. All final arguments for a command points to address 0x0.
  • [33]—the finite state machine uses this bit to identify and assert the "start of packet" protocol signal.
  • [32]—the finite state machine uses this bit to identify and assert the "end of packet" protocol signal.
  • [31..0]—The command header or argument that the design example sends to the Mailbox Client with Avalon® Streaming Interface IP.
u_avst_fsm_rsp

This module receives the response from the Mailbox Client with Avalon® Streaming Interface IP. The module handles the Avalon® streaming interface protocol and stores the header and arguments from the response in a FIFO. The design example exposes the read interface of the FIFO the u_control_sys module so you can access through the Intel® Quartus® Prime System Console.

  • You can access the master reset signal for the system through an In-System Sources and Probes instance. By default, the system is in the reset state.
  • The same In-System Sources and Probes instance connects to a heartbeat counter. Therefore, you must verify that the system has a free running clock.
  • A 100 MHz clock constrains all the design example logic.
  • The protocol finite state machine of the design example can handle only a single command at a time. Before sending the next command, wait until the system has stored the response from the previous command in the response FIFO.

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