4.4.3. Temperature Reading Design Example Description
All the Intel® Quartus® Prime System Console read and write commands control a set of parallel I/O IPs that select a command for the Mailbox Client with Avalon® Streaming Interface IP to execute. At the same time, the parallel I/O IPs control a FIFO IP that stores all the Mailbox Client with Avalon® Streaming Interface IP responses.
This module connects to a four-bit wide bus that selects a command for a finite state machine to send to the Mailbox Client with Avalon® Streaming Interface IP. The available commands are hardcoded in a look-up table (LUT) modeled in the command_rom.sv file. You can modify the LUT to edit existing commands or include new commands.
Command LUT ROM bit order:
This module receives the response from the Mailbox Client with Avalon® Streaming Interface IP. The module handles the Avalon® streaming interface protocol and stores the header and arguments from the response in a FIFO. The design example exposes the read interface of the FIFO the u_control_sys module so you can access through the Intel® Quartus® Prime System Console.
- You can access the master reset signal for the system through an In-System Sources and Probes instance. By default, the system is in the reset state.
- The same In-System Sources and Probes instance connects to a heartbeat counter. Therefore, you must verify that the system has a free running clock.
- A 100 MHz clock constrains all the design example logic.
- The protocol finite state machine of the design example can handle only a single command at a time. Before sending the next command, wait until the system has stored the response from the previous command in the response FIFO.