Agilex™ 7 Power Management User Guide

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ID 683373
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Management Overview 2. Agilex™ 7 Power Basics 3. Agilex™ 7 Power and I/O State Sequencing 4. Agilex™ 7 Sensor Monitoring System 5. Agilex™ 7 Power Optimization Techniques and Features 6. Document Revision History for the Agilex™ 7 Power Management User Guide
1. Agilex™ 7 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 7 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 7 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Power-Down Sequence Requirements for Agilex™ 7 Devices with E-Tile 3.4. Power-Down Sequence Requirements for the Agilex™ 7 M-Series Devices 3.5. Floating Voltage 3.6. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in GPIO, HPS, SDM Banks, and UIB Subsystem During Power Sequencing
3.6. Power-On Reset x
3.6.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 7 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations 4.4. Temperature Reading Design Example
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.2.3. Temperature Sensor Locations x
4.2.3.1. Getting Approximate Locations of the Transceiver Banks
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Temperature Monitor Design Guidelines 4.3.3. Transceiver Tile Local Temperature Sensor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 7 Remote TSD 4.3.5. Guidelines: Reading the R-Tile Local Temperature Sensor
4.4. Temperature Reading Design Example x
4.4.1. Directory Structure 4.4.2. Hardware and Software Requirements 4.4.3. Temperature Reading Design Example Description 4.4.4. Using the Temperature Reading Design Example 4.4.5. Verifying the Interaction between the Design Example and the Mailbox Client with Avalon® Streaming Interface IP
4.4.4. Using the Temperature Reading Design Example x
4.4.4.1. Opening the Temperature Reading Design Example 4.4.4.2. Compiling the Temperature Reading Design Example and Generating the Software Object File 4.4.4.3. Programming and Starting Up the Temperature Reading Design Example 4.4.4.4. Sending Commands to the Temperature Reading Design Example
4.4.4.4. Sending Commands to the Temperature Reading Design Example x
4.4.4.4.1. Default Commands for the Temperature Reading Design Example
5. Agilex™ 7 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Agilex™ 7 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Agilex™ 7 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Agilex™ 7 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Agilex™ 7 Power Management Overview
2. Agilex™ 7 Power Basics
3. Agilex™ 7 Power and I/O State Sequencing
4. Agilex™ 7 Sensor Monitoring System
5. Agilex™ 7 Power Optimization Techniques and Features
6. Document Revision History for the Agilex™ 7 Power Management User Guide

5.1.4.1.2. Power Management and VID Parameters

You can use the following parameters to configure the Power Management and VID interface if the VID operation is in the PMBus Master mode.
Table 28.  Power Management and VID Parameters
Parameters Value Description
Bus speed mode 24 100 KHz Bus speed mode of PMBus interface when operating in the PMBus Master mode.
400 KHz
Slave device type 24 ISL682XX

Supported device types.

Altera recommends you to use one of the slave device type listed in the drop-down menu that has been tested with the Altera® FPGA tools. If you are not using one of the slave device type listed in the drop-down menu, select Other option. When you select Other option, refer to Table: SmartVID Regulator Requirements, Table: Supported Voltage Output Format for Agilex™ 7 Devices with –V, –E, and –X Power Options, and Table: Supported Commands for the PMBus Master Mode and voltage regulator guidelines for the voltage regulator related requirements and details.
ISL69260
LTM4677
PXE1410CDM_G005
XDPE12284C
XDPE15284D
LTC3888-1
Device address in PMBus Slave mode 25 7-bit hexadecimal value Device address in the PMBus Slave mode.
Number of slave devices 1 to 7, or All Indicates the number of voltage regulator in the system.
PMBus device 0 slave address 24 7-bit hexadecimal value

External power regulator address.

This parameter must be non-zero when you are using the PMBus Master mode.
PMBus device 1 slave address 24 7-bit hexadecimal value External power regulator address.
PMBus device 2 slave address 24 7-bit hexadecimal value External power regulator address.
PMBus device 3 slave address 24 7-bit hexadecimal value External power regulator address.
PMBus device 4 slave address 24 7-bit hexadecimal value External power regulator address.
PMBus device 5 slave address 24 7-bit hexadecimal value External power regulator address.
PMBus device 6 slave address 24 7-bit hexadecimal value External power regulator address.
PMBus device 7 slave address 24 7-bit hexadecimal value External power regulator address.
Voltage output format 24 26 Direct format

The voltage output format when the operation mode is PMBus Master.

If the voltage output format is the Direct format, you must set the following parameters:

  • Direct format coefficient m
  • Direct format coefficient b
  • Direct format coefficient R

If the voltage regulator is the Linear format, you must set the Linear format N parameter. 27

For more information about the parameters, refer to your selected voltage regulator data sheet.

For all voltage output format, you must also select the correct "translated voltage output unit".
Linear format
Direct format coefficient m 24 Signed integer: -32768 to 32767 Direct format coefficient m of the slave device type when the operation mode is PMBus Master. For more information about the coefficient value, refer to the respective voltage regulator data sheet.
Direct format coefficient b 24 Signed integer: -32768 to 32767 Direct format coefficient b of the slave device type when the operation mode is PMBus Master. For more information about the coefficient value, refer to the respective voltage regulator data sheet.
Direct format coefficient R 24 Signed integer: -128 to 127 Direct format coefficient R of the slave device type when the operation mode is PMBus Master. For more information about the coefficient value, refer to the respective voltage regulator data sheet.
Linear format N 24 Signed integer: –16 to 15 Output voltage command when the voltage output format is set to the Linear format.
Translated voltage value unit 24 millivolts Indicates the translated output voltage is in millivolts (mV) or volts (V).
volts
Enable PAGE command 24 Enable By enabling the PAGE command, the FPGA PMBus Master uses the PAGE command to set all the output channels (0xFF) on registered regulator modules to respond to VOUT_COMMAND. If only specified output channels on registered regulator modules must respond to VOUT_COMMAND, enter the corresponding page value (0x00 – 0xFF).
Disable
Enable status_byte for polling 28 Enable

By enabling the STATUS_BYTE polling in the master mode, the firmware sends the STATUS_BYTE command for every 500 ms. This allows the firmware to analyze the error and put it into the EMQ.
Disable
Voltage Monitor Source 28 Voltage Regulator

Specify the voltage monitor source to verify the voltage accuracy.

  • Select Voltage Regulator (default) if you want the voltage reading to come from the voltage regulator.
  • Select Internal VADC if you want the voltage reading to come from the FPGA internal VADC.
  • Select Omitted if you do not want to perform any voltage reading.
Internal VADC
Omitted
Related Information
24 This parameter is used for the PMBus Master mode.
25 This parameter is used for the PMBus Slave mode.
26 The Auto Discovery format is no longer available in the GUI selection for the Agilex™ 7 devices starting from the Quartus® Prime software version 22.2 onwards. When migrating your design project from the Quartus® Prime software version 22.1 (or older) to the Quartus® Prime software version 22.2 (or later), you can select either the Direct format or Linear format listed in the GUI.
27 N is the exponent of a 5-bit two's compliment integer.
28 This feature is available in the Advanced Power Management & VID Options setting from the Quartus® Prime Pro Edition software version 24.3 onwards. Select More Options in the Power Management & VID Options to access this feature.
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