Intel Agilex® 7 Power Management User Guide

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ID 683373
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 Power Management Overview 2. Intel Agilex® 7 Power Basics 3. Intel Agilex® 7 Power and I/O State Sequencing 4. Intel Agilex® 7 Sensor Monitoring System 5. Intel Agilex® 7 Power Optimization Techniques and Features 6. Document Revision History for the Intel Agilex® 7 Power Management User Guide
1. Intel Agilex® 7 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Intel Agilex® 7 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Intel® FPGA Power and Thermal Calculator 2.4. Power Analyzer
3. Intel Agilex® 7 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Power-Down Sequence Requirements for Intel Agilex® 7 Devices with E-Tile 3.4. Floating Voltage 3.5. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing
3.5. Power-On Reset x
3.5.1. Power Supplies Monitored by the POR Circuitry
4. Intel Agilex® 7 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations 4.4. Temperature Reading Design Example
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.2.3. Temperature Sensor Locations x
4.2.3.1. Getting Approximate Locations of the Transceiver Banks
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Temperature Monitor Design Guidelines 4.3.3. Transceiver Tile Local Temperature Sensor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Intel Agilex® 7 Remote TSD 4.3.5. Guidelines: Reading the R-Tile Local Temperature Sensor
4.4. Temperature Reading Design Example x
4.4.1. Directory Structure 4.4.2. Hardware and Software Requirements 4.4.3. Temperature Reading Design Example Description 4.4.4. Using the Temperature Reading Design Example 4.4.5. Verifying the Interaction between the Design Example and the Mailbox Client with Avalon® Streaming Interface IP
4.4.4. Using the Temperature Reading Design Example x
4.4.4.1. Opening the Temperature Reading Design Example 4.4.4.2. Compiling the Temperature Reading Design Example and Generating the Software Object File 4.4.4.3. Programming and Starting Up the Temperature Reading Design Example 4.4.4.4. Sending Commands to the Temperature Reading Design Example
4.4.4.4. Sending Commands to the Temperature Reading Design Example x
4.4.4.4.1. Default Commands for the Temperature Reading Design Example
5. Intel Agilex® 7 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Intel® Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Intel Agilex® 7 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Intel Agilex® 7 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting The STATUS_BYTE Polling The Importance of Safety Limits Settings in the Voltage Regulator
5.1.4. Intel Agilex® 7 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Intel Agilex® 7 Power Management Overview
2. Intel Agilex® 7 Power Basics
3. Intel Agilex® 7 Power and I/O State Sequencing
4. Intel Agilex® 7 Sensor Monitoring System
5. Intel Agilex® 7 Power Optimization Techniques and Features
6. Document Revision History for the Intel Agilex® 7 Power Management User Guide
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5.1.2.4. Fault Management and Error Reporting

The SDM firmware has the capability to detect error, fault, or warning in the PMBus throughout the initialization and monitor states. The firmware analyzes any error and put it into the Error Message Queue (EMQ). During configuration, the CONFIG_STATUS mailbox command notifies you about the error.

In the master mode while running the monitor state, the SDM firmware queries the voltage regulator with a STATUS_BYTE command for every 500 ms. If the value returned from the STATUS_BYTE is not equal to zero, it indicates an error, fault, or warning within the voltage regulator. This firmware reports the error through the EMQ and assert the SEU_ERROR pin to notify you of this error.

In the slave mode, the SDM firmware asserts the PWRMGT_ALERT signal whenever an error occurs. The external PMBus master has to initiate the ARA flow to handshake with the FPGA to read the error from the firmware.

The STATUS_BYTE Polling

The STATUS_BYTE polling is an optional feature. To change the setting of the STATUS_BYTE polling, refer to the Specifying Power Management and VID Parameters and Option section and Table: Power Management and VID Parameters.

Figure 28. Fault Management and Error Reporting
Note: The polling of the STATUS_BYTE every 500 ms in the master mode is applicable when you select the voltage regulator that has been validated by Intel® . If you select "Others" in the Intel® Quartus® Prime GUI, the STATUS_BYTE polling is disabled.

The following table shows the error of the STATUS_BYTE based on the return bit.

Table 26.   STATUS_BYTE Error Definition
Command Error Definition
STATUS_BYTE (78h) Bit[7]: Busy, unable to respond
Bit[6]: Off, not enabled
Bit[5]: Output over voltage fault occurred
Bit[4]: Output over current fault occurred
Bit[3]: Input under voltage fault occurred
Bit[2]: Temperature fault or warning occurred
Bit[1]: Communication, memory, or logic fault occurred
Bit[0]: The fault occurred that are not listed above

Each bit returns from the STATUS_BYTE indicate a different error occurring in the voltage regulator and firmware reports each of them into the EMQ. For example, a value of 0x6 (b'0000_0110) returns from the STATUS_BYTE read reports that the voltage regulator is having communication, memory, or logic fault and temperature fault or warning asserted, the firmware inputs there 2 error entries into the EMQ for each of the error or fault occurred.

The Importance of Safety Limits Settings in the Voltage Regulator

You must program non-volatile memory (NVM) in the voltage regulator correctly to ensure the error flag is not asserted incorrectly for the expected operating condition.

For Intel Agilex® 7 SmartVID devices, VCC and VCCP operate within the 0.70 V to 0.90 V voltage range. The following is the example settings that works for this voltage range. You may revise the settings based on your system requirements. 

VOUT_OV_WARN_LIMIT to VID_MAX 927mV
VOUT_OV_FAULT_LIMIT to VID_MAX 930mV
VOUT_MAX to VID_MAX 950mV
VOUT_UV_WARN_LIMIT to VID_MIN 690mV
VOUT_UV_FAULT_LIMIT to VID_MIN 680mV

Limit should be wider or larger than the expected operating conditions, but within the absolute maximum rating for the device. For more information, refer to the Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series .

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