Intel® Agilex™ Power Management User Guide

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ID 683373
Date 9/06/2022
Public
Document Table of Contents

3.2. Power-Up Sequence Requirements

The power rails in the Intel® Agilex™ devices are divided into three groups.

The following figure shows the voltage groups of the Intel® Agilex™ devices and their required power-up sequence.

Figure 2. Power-Up Sequence for the Intel® Agilex™ Devices
Note: VCCBAT is not in any of the groups below. VCCBAT does not have any sequence requirements. VCCBAT holds the content of the security keys.

For more information about the VCCBAT connection guidelines and power supply sharing guidelines, refer to the Intel® Agilex™ Device Family Pin Connection Guidelines.

Table 3.  Voltage Rails Group
Power Group FPGA Core and Hard Processor System (HPS) Additional Voltage Rails
E-Tile P-Tile F-Tile R-Tile
Group 1

VCC

VCCP

VCCH

VCCL_SDM

VCCH_SDM

VCCPLLDIG_SDM

VCCL_HPS

VCCPLLDIG_HPS

VCCRT_GXE

VCC_HSSI_GXE 1

VCCRTPLL_GXE

VCC_HSSI_GXP

VCCRT_GXP

VCCFUSE_GXP

VCC_HSSI_GXF

VCCERT_FGT_GXF

VCCERT1_FHT_GXF

VCCERT2_FHT_GXF

VCC_HSSI_GXR

VCCE_PLL_GXR

VCCE_DTS_GXR

VCCRT_GXR

Group 2

VCCPT

VCCPLL_SDM

VCCADC

VCCPLL_HPS

VCCH_GXE 1

VCCCLK_GXE 1

VCCH_GXP

VCCCLK_GXP

VCCFUSECORE_GXF

VCCFUSEWR_GXF

VCCCLK_GXF

VCCH_FGT_GXF

VCCEHT_FHT_GXF

VCCED_GXR

VCCCLK_GXR

VCCH_FUSE_GXR

VCCH_GXR

Group 3

VCCA_PLL 2

VCCRCORE 2

VCCIO_PIO_SDM

VCCIO_PIO

VCCFUSEWR_SDM

VCCIO_SDM

VCCIO_HPS

All power rails in Group 1 must ramp up (in any order) to a minimum of 90% of their respective nominal voltage before the power rails from Group 2 can start ramping up. The power rails within Group 2 can ramp up in any order after the last power rail in Group 1 ramps to the minimum threshold of 90% of its nominal voltage. All power rails in Group 2 must ramp to a minimum threshold of 90% of their nominal value before the Group 3 power rails can start ramping up. The power rails within Group 3 can ramp up in any order after the last power rail in Group 2 ramps up to a minimum threshold of 90% of their full value. For more information, refer to the Intel® Agilex™ Device Family Pin Connection Guidelines.

All power rails must ramp up monotonically. The power-up sequence must meet the POR delay time. For the POR specifications of the Intel® Agilex™ devices, refer to the POR Specifications section in the Intel® Agilex™ Device Data Sheet.

For configuration via protocol (CvP), the total tRAMP must be less than 10 ms from the first power supply ramp-up to the last power supply ramp-up. For the tRAMP specifications, refer to the Recommended Operating Conditions section in the Intel® Agilex™ Device Data Sheet.

For Intel® Agilex™ devices, there is no power-down sequence requirement, except for Intel® Agilex™ devices with E-tile.

For Intel® Agilex™ devices without E-tile, Intel® recommends that you reverse the power-up sequence when you power down your device.

1 For Intel® Agilex™ devices with E-tile, these voltage rails must follow the power-down sequence. For more information, refer to the Power-Down Sequence for the Intel® Agilex™ Devices with E-Tile figure.
2 For Intel® Agilex™ production devices and ES (except 2486A package) devices, VCCA_PLL and VCCRCORE are part of power Group 3. For Intel® Agilex™ ES (2486A package) devices, VCCA_PLL and VCCRCORE are part of power Group 2.

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