3.2. Power-Up Sequence Requirements
The following figure shows the voltage groups of the Intel® Agilex™ devices and their required power-up sequence.
For more information about the VCCBAT connection guidelines and power supply sharing guidelines, refer to the Intel® Agilex™ Device Family Pin Connection Guidelines.
|Power Group||FPGA Core and Hard Processor System (HPS)||Additional Voltage Rails|
All power rails in Group 1 must ramp up (in any order) to a minimum of 90% of their respective nominal voltage before the power rails from Group 2 can start ramping up. The power rails within Group 2 can ramp up in any order after the last power rail in Group 1 ramps to the minimum threshold of 90% of its nominal voltage. All power rails in Group 2 must ramp to a minimum threshold of 90% of their nominal value before the Group 3 power rails can start ramping up. The power rails within Group 3 can ramp up in any order after the last power rail in Group 2 ramps up to a minimum threshold of 90% of their full value. For more information, refer to the Intel® Agilex™ Device Family Pin Connection Guidelines.
All power rails must ramp up monotonically. The power-up sequence must meet the POR delay time. For the POR specifications of the Intel® Agilex™ devices, refer to the POR Specifications section in the Intel® Agilex™ Device Data Sheet.
For configuration via protocol (CvP), the total tRAMP must be less than 10 ms from the first power supply ramp-up to the last power supply ramp-up. For the tRAMP specifications, refer to the Recommended Operating Conditions section in the Intel® Agilex™ Device Data Sheet.
For Intel® Agilex™ devices, there is no power-down sequence requirement, except for Intel® Agilex™ devices with E-tile.
For Intel® Agilex™ devices without E-tile, Intel® recommends that you reverse the power-up sequence when you power down your device.
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