2024.11.25 |
- Updated the note about VCCBAT in Power-Up Sequence Requirements.
- Added OSC_CLK_1 requirement in Guidelines for I/O Pins in GPIO, HPS, SDM Banks, and UIB Subsystem During Power Sequencing.
- Added temperature sensor locations availability for Agilex™ 7 I-Series R29D and R31E devices in Table: Temperature Sensor Locations Availability—Transceivers and HBM2E Tiles.
- Revised power rail name VCCH_FUSE_GXR to VCCHFUSE_GXR in Table: Voltage Rails Group for the Agilex™ 7 F-Series and I-Series Devices and Table: Voltage Rails Group for the Agilex™ 7 M-Series Devices.
- Updated Table: Power Management and VID Parameters:
- Added new parameter—Voltage Monitor Source.
- Updated parameter value for Slave device type from LTC3888 to LTC3888-1.
- Updated the description for the Slave device type parameter.
- Added SDM_IO9 to the list of values for the Use PWRMGT_ALERT output parameter in Table: Configuration Pin Parameters.
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2024.07.08 |
- Added guidelines for UIB subsystem in the Guidelines for I/O Pins in GPIO, HPS, SDM Banks, and UIB Subsystem During Power Sequencing section.
- Updated Figure: Relationship Between tRAMP and POR Delay.
- Updated the Catastrophic Trip Signal information in the Local Temperature Sensor section.
- Added temperature sensor locations availability for Agilex™ 7 M-Series R47B and R31B devices in Table: Temperature Sensor Locations Availability—Transceivers and HBM2E Tiles.
- Updated the footnote in sequence 9 in Table: Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE=0 for clarity.
- Updated Table: Power Management and VID Parameters to include ISL69260 as one of the supported slave device types.
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2024.04.01 |
- Updated Power-Down Sequence Requirements for Agilex™ 7 Devices with E-Tile.
- Added new topic—Power-Down Sequence Requirements for the Agilex™ 7 M-Series Devices.
- Updated Power Supplies Monitored by the POR Circuitry:
- Added VCCBAT to the list of power supplies are monitored by the Agilex™ 7 POR circuitry.
- Added a note to VCCL_HPS to state that this power supply only gates HPS power-up.
- Updated Table: Temperature Sensor Locations Availability—Transceivers and HBM2E Tiles to clarify that different densities on the R24C package have different tile location support.
- Updated the description of the get_temperature_3 command routine in Table: Command Routines in the main.tcl Script to clarify that get_temperature_3 reads the local TSD 1 in core fabric location 7 instead of core fabric location 2.
- Updated Table: Supported Commands for the PMBus Master Mode:
- Added STATUS_WORD.
- Removed Default column.
- Updated PMBus Slave Mode:
- Updated topic for clarity.
- Updated PMBus transaction type for CLEAR_FAULTS from send byte to write byte in Table: Supported Commands for the PMBus Slave Mode.
- Updated Table: Power Management and VID Parameters.
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2024.01.06 |
Updated the supported slave device types in Table: Power Management and VID Parameters. |
2023.12.04 |
- Added Table: Power Rails Floating Voltage for the Agilex™ 7 M-Series.
- Updated the supported slave device types in Table: Power Management and VID Parameters.
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2023.10.31 |
Added package R24D to the table listing the temperature sensor locations availability in the transceivers and HBM2E tiles. |
2023.09.29 |
Added the Getting Approximate Locations of the Transceiver Banks section. |
2023.07.17 |
- Added the STATUS_BYTE polling parameter in Table: Power Management and VID Parameters.
- Updated the Power-Up Sequence Requirements section.
- Updated the Fault Management and Error Reporting section.
- Updated The STATUS_BYTE Polling section.
- Updated Figure: Flow between the PMBus Voltage Regulator and FPGA in the PMBus Master Mode.
- Updated Figure: Fault Management and Error Reporting.
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2023.07.05 |
- Updated the ALERT_n guidelines in the Fault Management and Error Reporting section.
- Updated Table: Voltage Rails Group for the Agilex™ 7 M-Series Devices.
- Removed the note about restricted support for Agilex™ 7 M-Series FPGAs.
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2023.04.03 |
- Added support for Intel Agilex® 7 M-Series FPGAs.
- Added guidelines for reading the R-Tile local temperature sensor.
- Updated the Power-Up Sequence Requirements section.
- Updated the Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing section.
- Updated the Power-On Reset section.
- Updated the Power Supplies Monitored by the POR Circuitry section.
- Updated the SmartVID Standard Power Devices section.
- Updated the PMBus Slave Mode section.
- Updated Table: Power Rails Floating Voltage for the Agilex™ 7 F-Series and I-Series.
- Updated Table: The PMBus Master and Slave Modes Interfaces for the Agilex™ 7 Devices.
- Updated the Specifying Power Management and VID Parameters and Options section.
- Updated Table: Power Management and VID Parameters to include the supported voltage output format.
- Updated the description of the Use PWRMGT_ALERT output parameter in Table: Configuration Pin Parameters.
- Updated Figure: PMBus Slave Mode.
- Updated Figure: Fault Management and Error Reporting.
- Updated the topic about the temperature sensor locations:
- Updated the temperature sensing diode locations figure to show all possible locations for all Intel Agilex® 7 devices.
- Added tables listing the availability of the temperature sensors in different Intel Agilex® 7 series, densities, and packages.
- Removed Table: Stage Flow for the External PMBus Master without the PWRMGT_ALERT Signal and STATUS_BYTE=0.
- Removed Table: Stage Flow for the External PMBus Master without the PWRMGT_ALERT Signal and STATUS_BYTE is not Equal to 0.
- Removed Figure: Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode without PWRMGT_ALERT .
- Removed Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram without the PWRMGT_ALERT Signal.
- Retitled the document from Intel® Agilex™ 7 Power Management User Guide: F-Series and I-Series to Intel Agilex® 7 Power Management User Guide.
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2023.02.20 |
- Added the AGI 041 device.
- Updated product family name to "Intel® Agilex™ 7".
- Retitled the document from Intel® Agilex™ F-Series and I-Series Power Management User Guide to Intel® Agilex™ 7 Power Management User Guide: F-Series and I-Series.
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2022.12.19 |
- Added the Floating Voltage section.
- Updated the document title from Intel® Agilex™ Power Management User Guide to Intel® Agilex™ F-Series and I-Series Power Management User Guide.
- Updated the VID-fused value in the SmartVID Feature Implementation in Intel® Agilex™ Devices section.
- Updated the PMBus Master Mode section.
- Updated the default value of the VOUT_MODE command and the PMBus transaction type of the CLEAR_FAULTS command in Table: Supported Commands for the PMBus Master Mode.
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2022.09.06 |
Updated the Multi-Master Mode section. |
2022.08.08 |
Updated the F-Tile and R-Tile bank names for location 7 in the table listing the local temperature sensor locations and corresponding transceiver bank names. |
2022.06.21 |
- Updated the topic about the temperature sensor locations:
- Updated the list of devices for each location diagram.
- Added a table listing the local temperature sensor locations and corresponding transceiver bank names.
- Updated Table: Voltage Rails Group.
- Updated Figure: Flow between the PMBus Voltage Regulator and FPGA in the PMBus Master Mode.
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2022.05.27 |
Removed instances of Enpirion from Choosing a Power Tree and Power Generation sections and Power Management and VID Parameters table. |
2022.04.15 |
- Updated the Power-Up Sequence Requirements section to include details for the VCCBAT power supply.
- Removed the VCCBAT power supply from the Power Supplies Monitored by the POR Circuitry section.
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2022.04.04 |
- Added the Fail Safe Mechanism section.
- Added the Fault Management and Error Reporting section.
- Added Figure: Flow between the PMBus Voltage Regulator and FPGA in the PMBus Master Mode.
- Updated the Clock Gating section.
- Updated the Intel® Agilex™ Power Management and VID Interface QSF Constraint Guide section.
- Updated Figure: Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode without PWRMGT_ALERT.
- Updated the VCCH_FGT_GXF and VCCEHT_FHT_GXF power rails in Table: Voltage Rails Group .
- Updated Table: Power Management and VID Parameters to include ISL682XX voltage regulator.
- Updated the descriptions of the figures showing the temperature sensing diode locations to clarify that each figure shows the top view of the die. In the Quartus® Prime Chip Planner, the view is flipped.
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2022.01.25 |
Updated the topic that shows the temperature sensor locations to clarify that the figures show the top view of the devices as shown in the Quartus® Prime Chip Planner. |
2021.12.13 |
Updated the VCCRCORE pin name. |
2021.10.29 |
- Added Table: Power Rails Status for Intel® Agilex™ Devices.
- Added Table: Stage Flow for the External PMBus Master without the PWRMGT_ALERT Signal and STATUS_BYTE=0.
- Added Table: Stage Flow for the External PMBus Master without the PWRMGT_ALERT Signal and STATUS_BYTE is not Equal to 0.
- Added Figure: Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode with PWRMGT_ALERT .
- Added Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram without the PWRMGT_ALERT Signal.
- Added Figure: Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode without PWRMGT_ALERT .
- Updated Table: Comparison of Power and Thermal Calculator and Quartus® Prime Power Analyzer Capabilities.
- Updated Table: Supported Commands for the PMBus Master Mode.
- Updated Table: Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE=0.
- Updated Table: Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE is not equals to 0.
- Updated Table: Configuration Pin Parameters.
- Updated Table: Power Management and VID Parameters.
- Updated Table: Local Temperature Sensor Locations and Equivalent Remote TSD Pin Names.
- Updated Figure: PMBus Slave Mode.
- Updated Figure: Temperature Sensing Diode Locations— Intel® Agilex™ AGF 006 and AGF 008.
- Updated Figure: Temperature Sensing Diode Locations— Intel® Agilex™ AGF 012, AGF 014, AGF019, AGF 022, AGF023, AGF 027, AGI019, AGI 022, AGI023, and AGI 027.
- Updated the Intel® Agilex™ Power Management Overview section.
- Updated the Catastrophic Trip Signal section.
- Updated the Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing section.
- Updated the Power-Down Sequence Requirements for Intel® Agilex™ Devices with E-Tile section.
- Updated the SmartVID Standard Power Devices section.
- Updated the PMBus Master Mode section.
- Updated the PMBus Slave Mode section.
- Updated the Specifying Power Management and VID Parameters and Options section.
- Removed the Intel® Agilex™ Power Management and VID Interface Getting Started section and merged the content into the Intel® Agilex™ Power Management and VID Implementation Guide section.
- Removed Figure: External PMBus Master Software Flow.
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2021.07.02 |
- Updated the SmartVID Standard Power Devices section.
- Updated the SmartVID Feature Implementation in Intel® Agilex™ Devices section.
- Updated the SDM Power Manager section.
- Updated the Temperature Compensation section.
- Updated Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram.
- Updated Figure: Temperature Compensation for SmartVID for Intel® Agilex™ Devices.
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2021.06.09 |
- Updated the catastrophic trip signal information. The signal now drives low when the temperature is higher than 120°C.
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2021.04.13 |
- Added information for temperature sensors in R-Tile and F-Tile transceivers.
- Added the Multi-Master Mode section.
- Added reference to the Stratix® 10 and Intel® Agilex™ SmartVID Debug Checklist.
- Added reference to the Intel® FPGA Power and Thermal Calculator Standalone and Intel® FPGA Power and Thermal Calculator User Guide.
- Updated the Power and Thermal Calculator .
- Updated the SmartVID Standard Power Devices section to include the –X power option.
- Updated Table: Supported Voltage Output Format for Intel Agilex Devices with the –V, –E, and –X Power Options.
- Updated the description of the slave device type and voltage output format parameters in Table: Power Management and VID Parameters.
- Updated Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram.
- Updated Figure: External PMBus Master Software Flow.
- Removed VCCBAT from Table: Voltage Rails Group.
- Removed the H-Tile support.
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2021.02.08 |
- Updated the topic about the voltage monitoring system to clarify about internal high-voltage rails.
- Added VCCR_CORE (channel 5) to the figure showing the Intel® Agilex™ voltage sensor.
- Corrected the TSD location numbers for reading the temperatures of the HPS and SDM blocks.
- Updated the footnotes to the table that lists the local temperature sensor locations to clarify that channel 0 returns the highest temperature in a location for any location that has more than one TSD.
- Added the temperature sensor error codes.
- Added the Temperature Reading design example section.
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2020.11.11 |
Updated the footnote for VCCA_PLL and VCCR_CORE in Table: Voltage Rails Group. |
2020.10.19 |
- Updated the SmartVID value and SmartVID programmed value terms to VID-fused value.
- Added the Power-Down Sequence Requirements for Intel® Agilex™ Devices with E-Tile or H-Tile section.
- Updated the Power-Up Sequence Requirements section to include details about the power-down sequence for E-Tile and H-Tile devices.
- Updated the SDM Power Manager section.
- Updated the PMBus Slave Mode section.
- Updated the Temperature Compensation section.
- Updated Table: Voltage Rails Group.
- Updated Table: Power Management and VID Parameters to update the description of the Slave device type and Enable PAGE command parameters.
- Added Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram.
- Added Figure: Power-Down Sequence for Intel® Agilex™ Devices with H-Tile.
- Added Figure: Power-Down Sequence for Intel® Agilex™ Devices with E-Tile.
- Updated Figure: Temperature Compensation for SmartVID for Intel® Agilex™ Devices.
- Removed note (2) from Figure: External PMBus Master Software Flow.
- Updated Example 1—Specifying the Power Management and VID Parameters through QSF Constraints.
- Updated the voltage monitor range to up to 1.10 V.
- Updated the figure showing the voltage monitor 7-bit unipolar transfer function.
- Updated the table that provides an overview of the local and remote temperature sensors.
- Updated the topic about the local temperature sensors.
- Updated the figures showing the TSD locations.
- Updated the table listing the temperature sensor locations, channels, and remote TSD pin names.
- Updated the topic about retrieving the local temperature sensor reading.
- Added guidelines topic about calibrating the external temperature sensing chip.
- Renamed "Mailbox Avalon® ST Client Intel® FPGA IP" to "Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP".
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2020.04.22 |
- Added the Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing section.
- Added the F-Tile and R-Tile power rails in the Voltage Rails Group table.
- Added VCCR_CORE power supply to the Power Supplies Monitored by the POR Circuitry section.
- Added the Supported Voltage Output Format for Intel® Agilex™ Devices with the –V and –E Power Options table.
- Updated the table that provides an overview of the local and remote temperature sensors to clarify that the local temperature sensor operates only in user mode.
- Updated the topic about the temperature sensor channels and locations:
- Updated the description from using "channels" to "locations".
- Updated the diagram showing the sensor locations.
- Updated the table listing the sensor locations and equivalent remote TSD pins.
- Added topic about retrieving the local temperature sensor reading.
- Updated the voltage monitor design guidelines to add VSIGP and VSIGN pins guideline.
- Added the E-Tile transceiver local temperature sensor design guidelines.
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2020.02.06 |
- Updated the PMBus Slave Mode section.
- Added VCC_HSSI_GXE , VCCRTPLL_GXE , VCCR_CORE , VCCIO_PIO_SDM , and VCCBAT power rails to the Voltage Rails Group table.
- Removed VCCRTPLL_CR3_GXE and VCCM_WORD power rails from the Voltage Rails Group table.
- Removed the Power Distribution section.
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2019.10.04 |
- Changed the Early Power Estimator (EPE) tool name to Power and Thermal Calculator.
- Added the Intel® Agilex™ Power Management and VID Interface QSF Constraint Guide section.
- Added ED8401, EM21XX, and EM22XX device selection in the slave device type parameters in the Power Management and VID Parameters table.
- Updated the power optimization information in the Intel® Agilex™ Power Management Overview section.
- Updated the Early Power Estimator (EPE) section.
- Updated the Power Supplies Monitored by the POR Circuitry section to remove the note on powering up VCCBAT when not using the volatile key.
- Updated the SmartVID Standard Power Devices section to update the voltage value for VCC and VCCP during power up.
- Updated the VCCA_PLL power rail from Group 2 to Group 3 in the Voltage Rails Group table.
- Updated the Stage Flow for the External Power Management Controller in the PMBus Slave Mode figure.
- Changed the voltage and temperature sensors IP support from Temperature Sensor and Voltage Sensor IPs to Mailbox Client and Mailbox Avalon® ST IPs.
- Updated the Local Temperature Sensor topic to add information about the catastrophic trip (nCATTRIP) signal.
- Added reference to the Intel® Agilex™ Design Guideline Training: IBIS AMI Link Simulation, PDN, EMIF Layout Guidelines.
- Removed the Power Dissipation and Thermal Considerations section.
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2019.04.02 |
Initial release. |