Intel Agilex® 7 Power Management User Guide

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ID 683373
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 Power Management Overview 2. Intel Agilex® 7 Power Basics 3. Intel Agilex® 7 Power and I/O State Sequencing 4. Intel Agilex® 7 Sensor Monitoring System 5. Intel Agilex® 7 Power Optimization Techniques and Features 6. Document Revision History for the Intel Agilex® 7 Power Management User Guide
1. Intel Agilex® 7 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Intel Agilex® 7 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Intel® FPGA Power and Thermal Calculator 2.4. Power Analyzer
3. Intel Agilex® 7 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Power-Down Sequence Requirements for Intel Agilex® 7 Devices with E-Tile 3.4. Floating Voltage 3.5. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing
3.5. Power-On Reset x
3.5.1. Power Supplies Monitored by the POR Circuitry
4. Intel Agilex® 7 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations 4.4. Temperature Reading Design Example
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.2.3. Temperature Sensor Locations x
4.2.3.1. Getting Approximate Locations of the Transceiver Banks
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Temperature Monitor Design Guidelines 4.3.3. Transceiver Tile Local Temperature Sensor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Intel Agilex® 7 Remote TSD 4.3.5. Guidelines: Reading the R-Tile Local Temperature Sensor
4.4. Temperature Reading Design Example x
4.4.1. Directory Structure 4.4.2. Hardware and Software Requirements 4.4.3. Temperature Reading Design Example Description 4.4.4. Using the Temperature Reading Design Example 4.4.5. Verifying the Interaction between the Design Example and the Mailbox Client with Avalon® Streaming Interface IP
4.4.4. Using the Temperature Reading Design Example x
4.4.4.1. Opening the Temperature Reading Design Example 4.4.4.2. Compiling the Temperature Reading Design Example and Generating the Software Object File 4.4.4.3. Programming and Starting Up the Temperature Reading Design Example 4.4.4.4. Sending Commands to the Temperature Reading Design Example
4.4.4.4. Sending Commands to the Temperature Reading Design Example x
4.4.4.4.1. Default Commands for the Temperature Reading Design Example
5. Intel Agilex® 7 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Intel® Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Intel Agilex® 7 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Intel Agilex® 7 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Intel Agilex® 7 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Intel Agilex® 7 Power Management Overview
2. Intel Agilex® 7 Power Basics
3. Intel Agilex® 7 Power and I/O State Sequencing
4. Intel Agilex® 7 Sensor Monitoring System
5. Intel Agilex® 7 Power Optimization Techniques and Features
6. Document Revision History for the Intel Agilex® 7 Power Management User Guide
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5.1.4.1. Specifying Power Management and VID Parameters and Options

  1. Create an Intel® Quartus® Prime project using the New Project Wizard available from the File menu.
  2. On the Assignments menu, click Device.
  3. On the Device dialog box, click Device and Pin Options.
  4. On the Device and Pin Options dialog box, click Configuration.
  5. On the Configuration page, specify the VID Operation mode. There are two modes available—PMBus Master and PMBus Slave.
  6. The PMBus modes consist of these pins—PWMGT_SDA, PWMGT_SCL, and PWRMGT_ALERT. To configure these pins, on the Configuration page, click Configuration Pin Options. The PWRMGT_ALERT pin is only available and is required to be used in the slave mode. For the configuration pin parameters, refer to Table: Configuration Pin Parameters.
  7. On the Configuration Pin dialog box, assign the appropriate SDM_IO pin to the power management pins. Click OK.
  8. On the Device and Pin Options dialog box, click Power Management and VID to specify the device settings if your device is in the PMBus Master mode. Click OK. For the power management and VID parameters, refer to Table: Power Management and VID Parameters.
This completes the SmartVID setup for the Intel Agilex® 7 device.

Section Content
Configuration Pin Parameters
Power Management and VID Parameters
Power Management and VID Interface QSF Constraint Guide

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