Agilex™ 7 Power Management User Guide

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ID 683373
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Management Overview 2. Agilex™ 7 Power Basics 3. Agilex™ 7 Power and I/O State Sequencing 4. Agilex™ 7 Sensor Monitoring System 5. Agilex™ 7 Power Optimization Techniques and Features 6. Document Revision History for the Agilex™ 7 Power Management User Guide
1. Agilex™ 7 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 7 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Intel® FPGA Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 7 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Power-Down Sequence Requirements for Agilex™ 7 Devices with E-Tile 3.4. Power-Down Sequence Requirements for the Agilex™ 7 M-Series Devices 3.5. Floating Voltage 3.6. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in GPIO, HPS, SDM Banks, and UIB Subsystem During Power Sequencing
3.6. Power-On Reset x
3.6.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 7 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations 4.4. Temperature Reading Design Example
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.2.3. Temperature Sensor Locations x
4.2.3.1. Getting Approximate Locations of the Transceiver Banks
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Temperature Monitor Design Guidelines 4.3.3. Transceiver Tile Local Temperature Sensor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 7 Remote TSD 4.3.5. Guidelines: Reading the R-Tile Local Temperature Sensor
4.4. Temperature Reading Design Example x
4.4.1. Directory Structure 4.4.2. Hardware and Software Requirements 4.4.3. Temperature Reading Design Example Description 4.4.4. Using the Temperature Reading Design Example 4.4.5. Verifying the Interaction between the Design Example and the Mailbox Client with Avalon® Streaming Interface IP
4.4.4. Using the Temperature Reading Design Example x
4.4.4.1. Opening the Temperature Reading Design Example 4.4.4.2. Compiling the Temperature Reading Design Example and Generating the Software Object File 4.4.4.3. Programming and Starting Up the Temperature Reading Design Example 4.4.4.4. Sending Commands to the Temperature Reading Design Example
4.4.4.4. Sending Commands to the Temperature Reading Design Example x
4.4.4.4.1. Default Commands for the Temperature Reading Design Example
5. Agilex™ 7 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Agilex™ 7 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Agilex™ 7 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Agilex™ 7 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Agilex™ 7 Power Management Overview
2. Agilex™ 7 Power Basics
3. Agilex™ 7 Power and I/O State Sequencing
4. Agilex™ 7 Sensor Monitoring System
5. Agilex™ 7 Power Optimization Techniques and Features
6. Document Revision History for the Agilex™ 7 Power Management User Guide

2.2. Power Estimation Basics

The Altera power analysis features, including the Intel® FPGA Power and Thermal Calculator tool and the Quartus® Prime software Power Analyzer, give you the ability to estimate power consumption from early design concept through design implementation, as shown in the following figure.

As you provide more details about your design characteristics, estimation accuracy is improved. Altera recommends that you switch from the Intel® FPGA Power and Thermal Calculator to the Power Analyzer in the Quartus® Prime software once your design is available. The Power Analyzer produces more accurate results because it has more detailed information about your design, including routing and configuration information about all the resources in your design.

The accuracy of the power model is determined on a per-power-rail basis for both the Power Analyzer and the Intel® FPGA Power and Thermal Calculator.

For most designs, the Power Analyzer and the Intel® FPGA Power and Thermal Calculator have the following accuracies, with final power models:

  • Power Analyzer—within 10% of silicon for the majority of power rails and the highest power rails, assuming accurate inputs and toggle rates.
  • Intel® FPGA Power and Thermal Calculator—within 15% of silicon for the majority of power rails and the highest power rails, assuming accurate inputs and toggle rates. Recommended margins are shown in the Report tab, only after device power model status is final.
Figure 1. Power Analysis from Design Concept Through Design Implementation
Table 1.  Comparison of Intel® FPGA Power and Thermal Calculator and Quartus® Prime Power Analyzer Capabilities
Characteristic Intel® FPGA Power and Thermal Calculator Quartus® Prime Power Analyzer
When to use Any time
Note: For post-fit power analysis, you get better results with the Quartus® Prime Power Analyzer.
Post-fit
Software requirements
  • The Quartus® Prime software
  • The Intel® FPGA Power and Thermal Calculator
    • Available in a standalone version which offers the same features as the Intel® FPGA Power and Thermal Calculator version integrated within the Quartus® Prime software
The Quartus® Prime software
Accuracy Medium Medium to very high
Data inputs
  • Resource usage estimates
  • Clock requirements
  • Environmental conditions
  • Toggle rates
  • Post-fit design
  • Clock requirements
  • Signal activity defaults
  • Environmental conditions
  • Register transfer level (RTL) simulation results (optional)
  • Post-fit simulation results (optional)
  • Signal activities per node or entity (optional)
Data outputs
  • Total thermal power dissipation
  • Thermal static power
  • Thermal dynamic power
  • Off-chip power dissipation
  • Current drawn from voltage supplies
  • Total thermal power dissipation
  • Thermal static power
  • Thermal dynamic power
  • Thermal I/O power
  • Thermal power by design hierarchy
  • Thermal power by block type
  • Thermal power dissipation by clock domain
  • Off-chip (non-thermal) power dissipation
  • Current drawn from voltage supplies
Level Two Title