Intel® Agilex™ Power Management User Guide

ID 683373
Date 9/06/2022
Public
Document Table of Contents

5.1.2.2. PMBus Slave Mode

Intel® Agilex™ devices can also be configured in the PMBus slave mode with an external power management controller acting as the PMBus master. The external power management controller that interact with Intel® Agilex™ devices over PMBus must support clock stretching. The external power management controller is responsible for driving all PMBus transactions, querying the FPGA for its target voltage requirements and interacting with the voltage regulators to configure them to the FPGA's target voltage.

For the PMBus slave mode with PWRMGT_ALERT, you must follow the guidelines listed below for the external PMBus flow:

  • Figure: Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode with the PWRMGT_ALERT Signal
  • Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram with PWRMGT_ALERT
  • Table: Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE = 0
  • Table: Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE is not Equal to 0

For the PMBus slave mode without PWRMGT_ALERT, you must follow the guidelines listed below for the external PMBus flow:

  • Figure: Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode without PWRMGT_ALERT
  • Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram without the PWRMGT_ALERT Signal
  • Table: Stage Flow for the External PMBus Master without the PWRMGT_ALERT Signal and STATUS_BYTE = 0
  • Table: Stage Flow for the External PMBus Master without the PWRMGT_ALERT Signal and STATUS_BYTE is not Equal to 0
Figure 24. PMBus Slave Mode
Table 17.  Supported Commands for the PMBus Slave Mode
Command Name Command Code Default PMBus Transaction Type Number of Bytes
CLEAR_FAULTS 03h Send byte 0
VOUT_MODE 20h 40h Read byte 1
VOUT_COMMAND 21h Read word 2
STATUS_BYTE 78h 00h Read byte 1
Figure 25. Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode with the PWRMGT_ALERT Signal
Table 18.  Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE=0
Sequence SDM PMBus Master Notes
1 Asserts the PWRMGT_ALERT signal
2 Detects the PWRMGT_ALERT signal
3 Initiates the ARA flow
4 Responds to the ARA flow and provides its address Only the device which has asserted the PWRMGT_ALERT signal in step 1 responds to the ARA flow by providing its address.
5 De-asserts the PWRMGT_ALERT signal The PWRMGT_ALERT signal is only de-asserted after the SDM responds with its address in the ARA flow.
6 Reads the STATUS_BYTE
7 Returns STATUS_BYTE=0 Indicates the FPGA voltage requires an update.
8 Sends CLEAR_FAULTS
9 Sends VOUT_COMMAND The VOUT_COMMAND must be received by the SDM within 200ms after the PWRMGT_ALERT signal is asserted. Failure to meet this requirement causes configuration error. 11
10 Receives the VOUT_COMMAND, responds with the target voltage Calculated based on the temperature, the VID fuse and the coefficient for the direct format (you need to specify this input).
11 Sets the voltage regulator to the target voltage in step size not greater than 10mV/10ms step
Table 19.  Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE is not equals to 0
Sequence SDM PMBus Master Notes
1 Asserts the PWRMGT_ALERT signal The SDM detects fault and asserts the PWRMGT_ALERT signal. 12
2 Detects the PWRMGT_ALERT signal
3 Initiates the ARA flow
4 Responds to the ARA flow and provides its address Only the device which has asserted the PWRMGT_ALERT signal in step 1 responds to the ARA flow by providing its address.
5 De-asserts the PWRMGT_ALERT signal The PWRMGT_ALERT signal is only de-asserted after the SDM responds with its address in the ARA flow.
6 Reads the STATUS_BYTE
7 Returns the STATUS_BYTE when not equal to 0 Indicates that other fault has occurred
8 Sends CLEAR_FAULTS To reset the STATUS_BYTE.
9 Reads the STATUS_BYTE To confirm that STATUS_BYTE=0.
10 External master to handle the faults
Figure 26. Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram with PWRMGT_ALERT
Figure 27. Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode without PWRMGT_ALERT
Note: The connection for the PWRMGT_ALERT pin is optional for the PMBus slave mode. If you do not connect the PWRMGT_ALERT pin, the external power regulator has to rely on the nCONFIG, nSTATUS, and INIT_DONE signals to perform the handshake flow between the FPGA device and the external PMBus Master device.
Table 20.  Stage Flow for the External PMBus Master without the PWRMGT_ALERT Signal and STATUS_BYTE=0
Sequence SDM PMBus Master Notes
1 nCONFIG high
2 Detects nSTATUS signal high PMBus Master should begin to send STATUS_BYTE command as soon as the nSTATUS signal is high.
3 Send STATUS_BYTE This should be done periodically for every 200 ms until it is acknowledged by the firmware.
4 Return STATUS_BYTE=0 Indicates the FPGA voltage requires an update.
5 Send CLEAR_FAULTS
6 Send VOUT_COMMAND Checks the target voltage change due to temperature compensation.
7 Receives VOUT_COMMAND with the target voltage Calculated based on the temperature, the VID fuse, and the coefficient for the direct format (you need to specify this input).
8 Sets the voltage regulator to the target voltage in step size not greater than 10 mV/10 ms step
Table 21.  Stage Flow for the External PMBus Master without the PWRMGT_ALERT Signal and STATUS_BYTE is not Equal to 0
Sequence SDM PMBus Master Notes
1 nCONFIG high
2 Detects nSTATUS signal high PMBus Master should begin to send STATUS_BYTE command as soon as the nSTATUS signal is high.
3 Send STATUS_BYTE This should be done periodically for every 200 ms until it is acknowledged by the firmware.
4 Return STATUS_BYTE is not equal to 0 Indicates that another fault has occurred.
5 Send CLEAR_FAULTS To reset the STATUS_BYTE.
6 Read STATUS_BYTE To confirm STATUS_BYTE is 0.
7 External Master to handle the faults
Figure 28. Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram without the PWRMGT_ALERT Signal

The Intel® Agilex™ device in the PMBus slave mode sends the VOUT_COMMAND value in the direct format only. To read the actual voltage value, use the following equation to convert the VOUT_COMMAND value from the Intel® Agilex™ device.

Figure 29. Direct Format Equation

The equation shows how to convert the direct format value where:

  • X, is the calculated, real value in mV;
  • m, is the slope coefficient, a 2-byte two's complement integer;
  • Y, is the 2-byte two's complement integer received from the Intel® Agilex™ device;
  • b, is the offset, a 2-byte two's complement integer;
  • R, is the exponent, a 1-byte two's complement integer

The following example shows how an external power management controller retrieves values from the Intel® Agilex™ device. Coefficients used in the VOUT_COMMAND are as follows:

  • m = 1
  • b = 0
  • R = 0

If the external power management controller retrieved a value of 0384h, it is equivalent to the following:

X = (1/1) x (0384h x 10-0 - 0) = 900 mV = 0.90 V

11 When there is an error triggered by the SDM because it did not receive the VOUT_COMMAND within the specified time, you must power cycle the device to recover from the error. If you do not power cycle the device to recover from the error, you cannot configure the device successfully.
12

The following faults can raise the PWRMGT_ALERT signal:

  • PMBUS_ERR_RD_TOO_MANY_BYTES (Error with the length of the PMBus/I2C message length)
  • PMBUS_ERR_WR_TOO_MANY_BYTES (Error with the length of the PMBus/I2C message length)
  • PMBUS_ERR_UNSUPPORTED_CMD (VOUT_COMMAND, VOUT_MODE, READ_STATUS, and CLEAR_FAULTS are the only supported commands in the PMBUS Slave Mode)
  • PMBUS_ERR_READ_FLAG (Received duplicate command before being able to respond to the first command)
  • PMBUS_ERR_INVALID_DATA (Invalid or malformed PMBus/I2C message)

If any of the above errors are detected, the PWRMGT_ALERT signal is raised and bit 1 of the status register is set.

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