Intel Agilex® 7 Power Management User Guide

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ID 683373
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 Power Management Overview 2. Intel Agilex® 7 Power Basics 3. Intel Agilex® 7 Power and I/O State Sequencing 4. Intel Agilex® 7 Sensor Monitoring System 5. Intel Agilex® 7 Power Optimization Techniques and Features 6. Document Revision History for the Intel Agilex® 7 Power Management User Guide
1. Intel Agilex® 7 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Intel Agilex® 7 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Intel® FPGA Power and Thermal Calculator 2.4. Power Analyzer
3. Intel Agilex® 7 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Power-Down Sequence Requirements for Intel Agilex® 7 Devices with E-Tile 3.4. Floating Voltage 3.5. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing
3.5. Power-On Reset x
3.5.1. Power Supplies Monitored by the POR Circuitry
4. Intel Agilex® 7 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations 4.4. Temperature Reading Design Example
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.2.3. Temperature Sensor Locations x
4.2.3.1. Getting Approximate Locations of the Transceiver Banks
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Temperature Monitor Design Guidelines 4.3.3. Transceiver Tile Local Temperature Sensor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Intel Agilex® 7 Remote TSD 4.3.5. Guidelines: Reading the R-Tile Local Temperature Sensor
4.4. Temperature Reading Design Example x
4.4.1. Directory Structure 4.4.2. Hardware and Software Requirements 4.4.3. Temperature Reading Design Example Description 4.4.4. Using the Temperature Reading Design Example 4.4.5. Verifying the Interaction between the Design Example and the Mailbox Client with Avalon® Streaming Interface IP
4.4.4. Using the Temperature Reading Design Example x
4.4.4.1. Opening the Temperature Reading Design Example 4.4.4.2. Compiling the Temperature Reading Design Example and Generating the Software Object File 4.4.4.3. Programming and Starting Up the Temperature Reading Design Example 4.4.4.4. Sending Commands to the Temperature Reading Design Example
4.4.4.4. Sending Commands to the Temperature Reading Design Example x
4.4.4.4.1. Default Commands for the Temperature Reading Design Example
5. Intel Agilex® 7 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Intel® Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Intel Agilex® 7 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Intel Agilex® 7 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Intel Agilex® 7 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Intel Agilex® 7 Power Management Overview
2. Intel Agilex® 7 Power Basics
3. Intel Agilex® 7 Power and I/O State Sequencing
4. Intel Agilex® 7 Sensor Monitoring System
5. Intel Agilex® 7 Power Optimization Techniques and Features
6. Document Revision History for the Intel Agilex® 7 Power Management User Guide
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5.1.2.2. PMBus Slave Mode

Intel Agilex® 7 devices can also be configured in the PMBus slave mode with an external power management controller acting as the PMBus master. The external power management controller that interact with Intel Agilex® 7 devices over PMBus must support clock stretching. The external power management controller is responsible for driving all PMBus transactions, querying the FPGA for its target voltage requirements and interacting with the voltage regulators to configure them to the FPGA's target voltage.

For the PMBus slave mode with PWRMGT_ALERT, you must follow the guidelines listed below for the external PMBus flow:

  • Figure: Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode with the PWRMGT_ALERT Signal
  • Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram with PWRMGT_ALERT
  • Table: Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE = 0
  • Table: Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE is not Equal to 0
Figure 24. PMBus Slave Mode
Table 23.  Supported Commands for the PMBus Slave Mode
Command Name Command Code Default PMBus Transaction Type Number of Bytes
CLEAR_FAULTS 03h — Send byte 0
VOUT_MODE 20h 40h Read byte 1
VOUT_COMMAND 21h — Read word 2
STATUS_BYTE 78h 00h Read byte 1
Figure 25. Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode with the PWRMGT_ALERT Signal
Table 24.  Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE=0
Sequence SDM PMBus Master Notes
1 Asserts the PWRMGT_ALERT signal — —
2 — Detects the PWRMGT_ALERT signal —
3 — Initiates the ARA flow —
4 Responds to the ARA flow and provides its address — Only the device which has asserted the PWRMGT_ALERT signal in step 1 responds to the ARA flow by providing its address.
5 De-asserts the PWRMGT_ALERT signal — The PWRMGT_ALERT signal is only de-asserted after the SDM responds with its address in the ARA flow.
6 — Reads the STATUS_BYTE —
7 Returns STATUS_BYTE=0 — Indicates the FPGA voltage requires an update.
8 — Sends CLEAR_FAULTS —
9 — Sends VOUT_COMMAND The VOUT_COMMAND must be received by the SDM within 200ms after the PWRMGT_ALERT signal is asserted. Failure to meet this requirement causes configuration error. 14
10 Receives the VOUT_COMMAND, responds with the target voltage — Calculated based on the temperature, the VID fuse and the coefficient for the direct format (you need to specify this input).
11 — Sets the voltage regulator to the target voltage in step size not greater than 10mV/10ms step —
Table 25.  Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE is not equals to 0
Sequence SDM PMBus Master Notes
1 Asserts the PWRMGT_ALERT signal — The SDM detects fault and asserts the PWRMGT_ALERT signal. 15
2 — Detects the PWRMGT_ALERT signal —
3 — Initiates the ARA flow —
4 Responds to the ARA flow and provides its address — Only the device which has asserted the PWRMGT_ALERT signal in step 1 responds to the ARA flow by providing its address.
5 De-asserts the PWRMGT_ALERT signal — The PWRMGT_ALERT signal is only de-asserted after the SDM responds with its address in the ARA flow.
6 — Reads the STATUS_BYTE —
7 Returns the STATUS_BYTE when not equal to 0 — Indicates that other fault has occurred
8 — Sends CLEAR_FAULTS To reset the STATUS_BYTE.
9 — Reads the STATUS_BYTE To confirm that STATUS_BYTE=0.
10 — External master to handle the faults —
Figure 26. Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram with PWRMGT_ALERT

The Intel Agilex® 7 devices in the PMBus slave mode sends the VOUT_COMMAND value in the direct format only. To read the actual voltage value, use the following equation to convert the VOUT_COMMAND value from the Intel Agilex® 7 devices.

Figure 27. Direct Format Equation

The equation shows how to convert the direct format value where:

  • X, is the calculated, real value in mV;
  • m, is the slope coefficient, a 2-byte two's complement integer;
  • Y, is the 2-byte two's complement integer received from the Intel Agilex® 7 devices;
  • b, is the offset, a 2-byte two's complement integer;
  • R, is the exponent, a 1-byte two's complement integer

The following example shows how an external power management controller retrieves values from the Intel Agilex® 7 devices. Coefficients used in the VOUT_COMMAND are as follows:

  • m = 1
  • b = 0
  • R = 0

If the external power management controller retrieved a value of 0384h, it is equivalent to the following:

X = (1/1) x (0384h x 10-0 - 0) = 900 mV = 0.90 V

14 When there is an error triggered by the SDM because it did not receive the VOUT_COMMAND within the specified time, you must power cycle the device to recover from the error. If you do not power cycle the device to recover from the error, you cannot configure the device successfully.
15

The following faults can raise the PWRMGT_ALERT signal:

  • PMBUS_ERR_RD_TOO_MANY_BYTES (Error with the length of the PMBus/I2C message length)
  • PMBUS_ERR_WR_TOO_MANY_BYTES (Error with the length of the PMBus/I2C message length)
  • PMBUS_ERR_UNSUPPORTED_CMD (VOUT_COMMAND, VOUT_MODE, READ_STATUS, and CLEAR_FAULTS are the only supported commands in the PMBUS Slave Mode)
  • PMBUS_ERR_READ_FLAG (Received duplicate command before being able to respond to the first command)
  • PMBUS_ERR_INVALID_DATA (Invalid or malformed PMBus/I2C message)

If any of the above errors are detected, the PWRMGT_ALERT signal is raised and bit 1 of the status register is set.

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