AN 886: Intel® Agilex™ Device Design Guidelines

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ID 683634
Date 8/26/2022
Public
Document Table of Contents

5.5. Transceiver Planning

There are four types of transceiver tiles available in Intel® Agilex™ FPGAs:
Note: For more information about F-Tile, contact your Intel® representative.
Note: Key: GPIO (LVDS) / E-Tile 28.9G (58G) / P-Tile Gen4 (16G_ PCIe* ) Example: If an entry in the table below contains 576(288)/24(12)/16, it means that 576 GPIO of which 288 are LVDS; twenty-four 28.9 NRZ channels and twelve 58G PAM4 channels; sixteen up to 16G/lane PCIe*
Table 45.   Intel® Agilex™ F-Series FPGAs with P-Tile and E-Tile Package Options and I/O Pins
Intel® Agilex™ F-Series Device Names R2068A 5 R2486A 6 R2486B 7
AGF004
AGF006
AGF008 576(288)/24(12)/16
AGF012 576(288)/24(12)/16 768(384)/16(8)/16 768(384)/24(12)/16
AGF014 576(288)/24(12)/16 768(384)/16(8)/16 768(384)/24(12)/16
AGF022 768(384)/24(12)/16
AGF027 768(384)/24(12)/16
Note: R2486A and R2486B are not package compatible or migratable.
For the R2486A package E-tile, the channel bondout uses all 16 channels that have access to the Ethernet Hard IP (EHIP)s. The 16 channels that have access to EHIPs are channels:
  • 0 - 3
  • 8 - 15
  • 20 - 23
Table 46.  Available E-Tile Transceiver Channels in Intel® Agilex™ FPGA Devices
Intel® Agilex™ F-Series Device Names Number of E-Tile Transceiver Channels Available E-Tile Transceiver Channel Locations
AGF 004
AGF 006
AGF 008 24 0 through 23
AGF 012 16 or 24

16 channels: 0,1,2,3,8,9,10,11,12,13,14,15,20,21,22,23

24 channels: 0 through 23

AGF 014 16 or 24

16 channels: 0,1,2,3,8,9,10,11,12,13,14,15,20,21,22,23

24 channels: 0 through 23

AGF 022 24 0 through 23
AGF 027 24 0 through 23
5 (E-Tile + P-Tile) (52 mm x 37.5 mm, Hex 1.0 mm pitch)
6 (E-Tile + P-Tile) (55 mm x 42.5 mm, Hex 1.0 mm pitch)
7 (E-Tile + P-Tile) (55 mm x 42.5 mm, Hex 1.0 mm pitch)

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