AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022

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Document Table of Contents Configuration Features

Table 64.  Configuration Features Checklist
Number Done? Checklist Item
1   Ensure your configuration scheme and board support the required features: RSU, single event upset (SEU) mitigation.

This section describes Intel® Agilex™ device configuration features and how they affect your design process.

Configuration Bitstream Compression

Configuration bitstream compression is always enabled in Intel® Agilex™ device configuration. The Intel® Quartus® Prime software generates configuration files with compressed configuration data. This compressed file reduces the storage requirements in the configuration device or flash memory, and decreases the time required to transmit the configuration bitstream to the Intel® Agilex™ device.

Due to compressed configuration bitstream, passive configuration schemes for example Avalon® -ST ×8, ×16, and ×32 may require the external configuration host to monitor the AVST_READY signal and pause sending configuration data when the AVST_READY low signal is detected.

SEU Mitigation

Dedicated circuitry is built into Intel® Agilex™ devices for error detection and correction. When enabled, this feature checks for SEUs continuously and automatically. This allows you to confirm that the configuration data stored in an Intel® Agilex™ device is correct and alerts the system to a configuration error.

When using the SEU mitigation features, an SDM pin is used to implement the SEU_ERROR function. This pin flags errors for your system to take appropriate actions. Prior to compiling your design, enable the SEU_ERROR function and select an unused SDM pin to implement the SEU_ERROR function in the Intel® Quartus® Prime software.


RSU implements device reconfiguration using dedicated RSU circuitry available in all Intel® Agilex™ devices.

For more information, refer to Intel® Agilex™ Configuration User Guide.