AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Document Table of Contents

9.6. Choosing the Bootloader Software

The typical Intel® Agilex™ SoC HPS boot flow is depicted in the figure below:

Figure 15. Typical Intel® Agilex™ SoC Boot Flow

The bootloader software is one of the most important components of your software development platform. The bootloader initializes the system and then loads and passes control to the next boot image which is either an operating system or a bare-metal application.

The Intel® Agilex™ SoC bootloader software is split into two different stages:
  • First Stage Bootloader (FSBL) – Loaded by the SDM from the FPGA configuration bitstream into the HPS side on-chip memory:
    • Provides essential initial hardware settings to configure the HPS
    • Software features to control the flash and peripheral components of the HPS
    • Utilities to enable early debugging and troubleshooting
  • Second Stage Bootloader (SSBL) – Loaded by FSBL into the DDRAM and potentially having significantly more capabilities than FSBL, such as: network access, command line interface and scripting support.
Several bootloaders are enabled for Intel® Agilex™ devices:
  • U-Boot Bootloader: Inherits several features available from the open source community and is popular with Linux* OS users. U-Boot bootloader is governed by GPL licensing.
  • UEFI Bootloader: Feature rich and popular with RTOS users and is governed by an open-source BSD style license.
  • ATF (ARM Trusted Firmware) Bootloader: Used by the UEFI and provides just the first stage bootloader. It uses a BSD-style license, and could be used to directly load a bare-metal application instead of a SSBL.

GUIDELINE: To select the right bootloader for your software development platform, use the latest version and familiarize yourself with the GPL and open-source BSD licenses and consider which licensing terms best suit your requirements.

A typical HPS system has hundreds of registers that must be set for a given configuration of the MPU subsystem, the network-on-chip interconnect component, the DDRAM memory, flash boot source and peripheral interfaces.

GUIDELINE: Given the amount of initialization settings that are required, it is not recommended to write a bootloader from scratch. The provided bootloader options contain optimum and default configuration settings for various parts of the HPS.

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