AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

5.1.5. HPS Pin Multiplexing Design Considerations

There is a total of 48 dedicated HPS I/O pins. The HPS component in Platform Designer offers pin multiplexing settings as well as the option to route most of the peripherals into the FPGA fabric.

GUIDELINE: Route the USB, EMAC and Flash interfaces to the HPS Dedicated I/O first, starting with USB.

Intel® recommends that you start by routing high speed interfaces such as USB, Ethernet, and flash to the Dedicated I/O first.

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