AN 886: Intel® Agilex™ Device Design Guidelines

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ID 683634
Date 8/26/2022
Public
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5.3.2.2. HPS EMIF I/O Locations

The Intel® Agilex™ EMIF for HPS IP includes default pin location assignments for all the external memory interface signals in constraint files created at IP generation time and read by Intel® Quartus® Prime Pro Edition software during design compilation.

GUIDELINE: Intel® recommends that you use these automated default pin location assignments as a starting point.

You may need to modify the default pinout to meet the restrictions shown in this section.

GUIDELINE: Verify the HPS memory controller I/O locations in the Intel® Quartus® Prime project pinout file in the “output_files” sub-folder before finalizing board layout.

By default, Intel® Quartus® Prime generates output reports, log files and programming files in the output_files subfolder of the project folder. See the .pin text file after compilation for the pinout for your design, including the pin locations for the HPS EMIF.

GUIDELINE: Make sure all I/O associated with the HPS memory interface are located within the active HPS EMIF I/O banks.

It is critical that you ensure all I/O necessary for a functioning HPS memory interface are located within the active banks for your HPS memory width.

For a description about the pin assignment and the restriction on I/O Bank Usage for Intel® Agilex™ EMIF IP with HPS, refer to the Intel® Agilex™ FPGA EMIF IP Overview.
Table 41.  HPS EMIF I/O Locations
EMIF Width Tile 3C Tile 3D
Top Bottom Top Bottom
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
16-bit GPIO GPIO NC 16-bit Data NC Addr/Command/RZQ/RefClk
16-bit + ECC GPIO GPIO NC 16-bit Data ECC Addr/Command/RZQ/RefClk
32-bit GPIO GPIO 32-bit Data NC Addr/Command/RZQ/RefClk
32-bit + ECC GPIO GPIO 32-bit Data ECC Addr/Command/RZQ/RefClk
64-bit GPIO (with restrictions) 64-bit Data NC Addr/Command/RZQ/RefClk
64-bit + ECC GPIO (with restrictions) 64-bit Data ECC Addr/Command/RZQ/RefClk
Note: NC = No Connect

Pin Assignments

  1. Within a single data lane (which implements a single x8 DQS group):
    • DQ pins must use pins at indices 0, 1, 2, 3, 8, 9, 10, 11. You may swap the locations between the DQ bits (that is, you may swap location of DQ[0] and DQ[3]) so long as the resulting pin-out uses pins at these indices only.
    • DM/DBI pin must use pin at index 6. There is no flexibility.
    • DQS_P must use pin at index 4, and DQS_N must use pin at index 5. There is no flexibility.
    • pin index 7 must be “no connect”.
  2. Assignment of data lanes must be as illustrated in the above figure. You are allowed to swap the locations of entire byte lanes (that is, you may swap locations of byte 0 and byte 1) so long as the resulting pin-out uses only the lanes permitted by your HPS EMIF configuration, as shown in the above figure.
  3. I/O Tile 3D, Bottom Bank Lanes 0, 1, and 2 must only be used for Address/Command/RZQ/REFCLK, otherwise “no connect”.
  4. If not using ECC, I/O Tile 3D, Bottom Bank Lane 3 must be “no connect”. If using ECC, the ECC DQS group must be in I/O Tile 3D, Bottom Bank Lane 3.
  5. You must not change placement of the address and command pins from the default placement.
  6. Place the ALERT# pin at I/O Tile 3D, Bottom Bank Lane 2, pin index 8 only, else “no connect”.
  7. HPS REFCLK_P must use I/O Tile 3D, Bottom Bank Lane 2, pin index 0. HPS REFCLK_N must use I/O Tile 3D, Bottom Bank Lane 2, pin index 1.
  8. RZQ must use I/O Tile 3D, Bottom Bank Lane 2, pin index 2.

DQ/DQS Group Placement

Configuration DQS Group Placement
16 bit Must be placed in I/O lanes Top[1:0] of Bank 3D
16 bit + ECC Must be placed in I/O lanes Top[1:0] of Bank 3D and Bottom[3] of Bank 3D
32 bit Must be placed in I/O lanes Top[3:0] of Bank 3D
32 bit + ECC Must be placed in I/O lanes Top[3:0] of Bank 3D and Bottom[3] of Bank 3D
64 bit Must be placed in I/O lanes Top[3:0] of Bank 3D and Bottom[3:0] of Bank 3C
64 bit + ECC Must be placed in I/O lanes Top[3:0] of Bank 3D and Bottom[3:0] of Bank 3C and Bottom[3] of Bank 3D
Note: In all cases, the DQ/DQS groups can be swapped around in the I/O banks shown.

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