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1. Introduction to the Intel® Agilex™ Device Design Guidelines
2. System Specification
3. Device Selection
4. Security Considerations
5. Design Entry
6. Board and Software Considerations
7. Design Implementation, Analysis, Optimization, and Verification
8. Debugging
9. Embedded Software Design Guidelines for Intel® Agilex™ SoC FPGAs
5.1.1. Firewall Planning
5.1.2. Boot And Configuration Considerations
5.1.3. HPS Clocking and Reset Design Considerations
5.1.4. Reset Configuration
5.1.5. HPS Pin Multiplexing Design Considerations
5.1.6. HPS I/O Settings: Constraints and Drive Strengths
5.1.7. Design Guidelines for HPS Interfaces
5.1.8. Interfacing between the FPGA and HPS
5.1.9. Implementing the Intel® Agilex™ HPS Component
7.1. Selecting a Synthesis Tool
7.2. Device Resource Utilization Reports
7.3. Intel® Quartus® Prime Messages
7.4. Timing Constraints and Analysis
7.5. Area and Timing Optimization
7.6. Preserving Performance and Reducing Compilation Time
7.7. Designing with Intel® Hyperflex™
7.8. Simulation
7.9. Power Analysis
7.10. Power Optimization
7.11. Design Implementation, Analysis, Optimization, and Verification Revision History
9.1. Overview
9.2. Golden Hardware Reference Design (GHRD)
9.3. Define Software Requirements
9.4. Define Software Architecture
9.5. Selecting Software Tools
9.6. Choosing the Bootloader Software
9.7. Selecting an Operating System for Your Application
9.8. Assembling Your Software Development Platform for Linux*
9.9. Assembling your Software Development Platform for Partner OS or RTOS
9.10. Driver Considerations
9.11. Boot And Configuration Considerations
9.12. System Reset Considerations
9.13. Flash Considerations
9.14. Develop Application
9.15. Test and Validate
9.16. Embedded Software Design Guidelines Revision History
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8.1.1. Planning Guidelines for Debugging Tools
Number | Done? | Checklist Item |
---|---|---|
1 | Select on-chip debugging schemes early to plan memory and logic requirements, I/O pin connections, and board connections. | |
2 | If you want to use Signal Probe incremental routing, the Signal Tap Embedded Logic Analyzer, Logic Analyzer Interface, In-System Memory Content Editor, In-System Sources and Probes, or Virtual JTAG IP core, plan your system and board with JTAG connections that are available for debugging. | |
3 | Plan for the small amount of additional logic resources used to implement the JTAG hub logic for JTAG debugging features. | |
4 | For debugging with the Signal Tap Embedded Logic Analyzer, reserve device memory resources to capture data during system operation. Ensure that the JTAG signals have a clean timing. | |
5 | Reserve I/O pins for debugging with Signal Probe or the Logic Analyzer Interface so you do not have to change the design or board to accommodate debugging signals later. | |
6 | Ensure the board supports a debugging mode where debugging signals do not affect system operation. | |
7 | Incorporate a pin header or mictor connector as required for an external logic analyzer or mixed signal oscilloscope. | |
8 | To use debug tools incrementally and reduce compilation time, ensure incremental compilation is on so you do not have to recompile the design to modify the debug tool. | |
9 | To use the Virtual JTAG IP core for custom debugging applications, instantiate it in the HDL code as part of the design process. | |
10 | To use the In-System Sources and Probes feature, instantiate the IP core in the HDL code. | |
11 | To use the In-System Memory Content Editor for RAM or ROM blocks, turn on the Allow In-System Memory Content Editor to capture and update content independently of the system clock option for the memory block in the IP catalog. |
If you intend to use any of the on-chip debugging tools, plan for the tool(s) when developing the system board, Intel® Quartus® Prime project, and design.
For more information about debug tools, please refer to Intel® Quartus® Prime Pro Edition User Guide: Debug Tools.
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