AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

5.1.7.4. Design Guidelines for Flash Interfaces

GUIDELINE: Connecting the QSPI flash to the SoC device.

The HPS does not have a QSPI flash controller. The HPS has access to the QSPI controller in the SDM.

For an example of Flash Memory implementation, refer to the Intel® Agilex™ F-Series Transceiver-SoC Development Kit Schematics .

GUIDELINE: In the Intel® Quartus® Prime Pro Edition GUI, select the configuration clock speed to match the capabilities of the QSPI flash device that you selected.

For more information about considerations when connecting QSPI flash to the SDM QSPI interface, refer to the Intel® Agilex™ Hard Processor System Technical Reference Manual.

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