8.2. On-Chip Debugging Tools
The Intel® Quartus® Prime portfolio of verification tools includes the following in-system debugging features:
- Signal Probe incremental routing—Quickly routes internal signals to I/O pins without affecting the routing of the original design. Starting with a fully routed design, you can select and route signals for debugging to either previously reserved or currently unused I/O pins.
- Signal Tap Embedded Logic Analyzer—Probes the state of internal and I/O signals without the use of external equipment or extra I/O pins, while the design is running at full speed in an FPGA device. Defining custom trigger-condition logic provides greater accuracy and improves the ability to isolate problems. It does not require external probes or changes to the design files to capture the state of the internal nodes or I/O pins in the design; all captured signal data is stored in the device memory until you are ready to read and analyze the data. The Signal Tap Embedded Logic Analyzer works best for synchronous interfaces. For debugging asynchronous interfaces, consider using Signal Probe or an external logic analyzer to view the signals more accurately. Signal Tap may affect routing of the original design.
- Logic Analyzer Interface—Enables you to connect and transmit internal FPGA signals to an external logic analyzer for analysis, allowing you to take advantage of advanced features in your external logic analyzer or mixed signal oscilloscope. You can use this feature to connect a large set of internal device signals to a small number of output pins for debugging purposes and it can multiplex signals with design I/O pins if required.
- In-System Memory Content Editor—Provides read and write access to in-system FPGA memories and constants through the JTAG interface, so you can test changes to memory content and constant values in the FPGA while the device is functioning in the system.
- In-System Sources and Probes—Sets up custom register chains to drive or sample the instrumented nodes in your logic design, providing an easy way to input simple virtual stimuli and capture the current value of instrumented nodes.
- Virtual JTAG Intel® FPGA IP core—Enables you to build your own system-level debugging infrastructure, including both processor-based debugging solutions and debugging tools in the software for system-level debugging. You can instantiate the SLD_VIRTUAL_JTAG Intel® FPGA IP core directly in your HDL code to provide one or more transparent communication channels to access parts of your FPGA design using the JTAG interface of the device.
- EMIF Debug Toolkit—Tcl-based graphical user interface communicating via a JTAG connection to enable external memory interface on the circuit board to retrieve calibration status and debug information. The Driver Margining feature of the tool kit allows you to measure margins on your memory interface using a driver with arbitrary traffic patterns. Tcl-based graphical user interface that provides access to memory calibration data gathered by the Nios® II sequencer, via a JTAG connection. The Toolkit allows you to mask ranks for calibration, and to request recalibration of the interface. The Driver Margining feature of the toolkit allows you to measure margins on the memory interface using a driver with arbitrary traffic patterns. The EMIF Toolkit can communicate with several different memory interfaces on the same device, but only one at a time.
- Transceiver Toolkit—Uses System Console technology to help FPGA and board designers validate transceiver link signal integrity real time in a system and improve board bring-up time. Test for bit-error rate (BER) while simultaneously running multiple links at your target data rate to validate your board design with Transceiver Toolkit. Tune transceiver analog settings for optimal link performance while using different test metrics to quantify results. Simultaneously test multiple devices across one or more boards using link tests in the Transceiver Toolkit GUI.
- P-Tile Toolkit—Provides support for an Avalon® -MM interface with DMA and is designed to optimize the performance of large-size data transfers. If you want to achieve maximum performance with small-size transfers, Intel recommends the use of an Avalon® -ST IP core like the P-Tile Avalon® -ST Hard IP for PCIe. P-Tile supports PCI Express* Gen4 in Endpoint, Root Port and TLP Bypass modes.
- SDM Debug Toolkit—The SDM Debug Toolkit provides access to the current status of the Intel® Agilex™ device.
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