6.1.6. Device Power-Up
|1||Design board for power-up: All Intel® Agilex™ GPIO pins are tri-stated until the device is configured and configuration pins drive out. The transceiver pins are at high impedance before the device periphery could get programmed. Once the periphery is programmed, the termination and Vcm are set immediately after transceiver calibration is complete.|
|2||Design voltage power supply ramps to be monotonic.|
|3||Set POR time to ensure power supplies are stable.|
|4||Design power sequencing and voltage regulators for best device reliability. Connect the GND between boards before connecting the power supplies.|
|5||Pull nSTATUS pin high to VCCIO_SDM. Ensure no external component to drive nSTATUS low during power up.|
The minimum current requirement for the power-on-reset (POR) supplies must be available during device power-up.
The Intel® Agilex™ device has Power-On-Reset circuitry, which keeps the device in a reset state until the power supply outputs are within the recommended operating range. The device must reach the recommended operating range within the maximum power supply ramp time. If the ramp time is not met, the device I/O pins and programming registers remain tri-stated and device configuration fails.
In Intel® Agilex™ devices, when the pin-selectable option (MSEL) is set to non FAST QSPI mode, a typical POR time setting of 4 ms or 100 ms is available.
Intel® Agilex™ devices have power-up sequencing requirements. You should consider the power-up timing and power-down timing for each rail in order to meet the power sequencing requirements.
Intel uses GND as a reference for I/O buffer designs. Connecting the GND between boards before connecting the power supplies prevents the GND on your board from being pulled up inadvertently by a path to power through other components on your board. A pulled-up GND could otherwise cause an out-of-specification I/O voltage or current condition with the Intel device.
All I/O pins in the SDM and the HPS bank, except VSIGP_0, VSIGN_0, VSIGP_1, VSIGN_1 and RREF_SDM, are in an undetermined state during device power up and power down.
All HPS data transactions should start after the device is fully powered up.
Input signals of all I/O pins, at any point during power up and power down, should not exceed the I/O buffer power supply rail of the bank where the I/O pin resides.
When using I/O pins in the GPIO bank, the pin voltage—when the device is not turned on or during power-up or power-down conditions must not exceed 1.2 V for both 1.2 V and 1.5 V VCCIO_PIO.
After the device is fully powered up, input signals of the I/O pin should not exceed the maximum DC input voltage specification as specified in the Intel® Agilex™ Device Data Sheet.