Visible to Intel only — GUID: ger1557106886292
Ixiasoft
Visible to Intel only — GUID: ger1557106886292
Ixiasoft
7.4.1. Recommended Timing Optimization and Analysis Assignments
Number | Done? | Checklist Item |
---|---|---|
1 | Turn on Optimize multi-corner timing on the Fitter Settings page in the Settings dialog box. | |
2 | Use create_clock and create_generated_clock to specify the frequencies and relationships for all clocks in your design. | |
3 | Use set_input_delay and set_output_delay to specify the external device or board timing parameters. | |
4 | Use derive_clock_uncertainty to automatically apply inter-clock, intra-clock, and I/O interface uncertainties. | |
5 | Use check_timing to generate a report on any problem with the design or applied constraints, including missing constraints. | |
6 | Use set_false_path or set_clock_groups for asynchronous paths. |
These assignments and settings are important for large designs such as those in Intel® Agilex™ devices.
When you turn on the Optimize multi-corner timing option, the design is optimized to meet its timing requirements at all timing process corners and operating conditions. Therefore, turning on this option helps create a design implementation that is more robust across PVT variations.
In your Timing Analyzer .sdc constraints file, apply the recommended constraints to your design.
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