AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

5.2.2.6. Clock Control Features

Table 38.  Clock Control Features Checklist
Number Done? Checklist Item
1   Use the clock control block for clock selection and power-down.

Intel® Agilex™ devices uses these clock control features: clock gating and clock divider. The clock from the I/O PLL output can be gated dynamically. These clock signals along with other clock sources go to the periphery distributed clock multiplexer (DCM). In the periphery DCM, the clock signal can either pass straight through, be gated by the root clock gate, or be divided by the clock divider.

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