220.127.116.11. Selecting HPS Boot Options
- FPGA Configuration First: The SDM configures the FPGA core and all the periphery I/O before loading the FSBL into the HPS on-chip RAM and releasing the HPS from reset. If any errors exist during initial configuration, the HPS is not released from reset.
- HPS First: The SDM only configures the I/O required for the HPS EMIF, and then loads the FSBL into the HPS on-chip RAM before releasing the HPS from reset. The FPGA core, as well as the other unused I/O, remain unconfigured. The HPS configures the rest of the FPGA.
Select a configuration and boot mode by selecting Assignments > Device > Device and Pin Options > HPS/FPGA configuration order tab in Intel® Quartus® Prime Pro Edition.
HPS First and FPGA First Boot Considerations
Guideline: HPS First Boot Mode Utilizes Early I/O Release
Follow the guidelines in this document to properly design your board and the SoC device pin out for the HPS EMIF interface for Early I/O Release.
For more information about the supported boot modes, refer to the Intel® Agilex™ SoC Boot User Guide and the "Boot and Configuration" section in the Intel® Agilex™ Hard Processor System Technical Reference Manual.
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