AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

9.11.1. Configuration Sources

The initial FPGA configuration and the HPS FSBL are part of the initial configuration bitstream, which can be obtained from several sources:

  • Avalon® -ST Data Source: An external Avalon® -ST master provides the bitstream.
  • JTAG Interface: An external JTAG master (usually driven by a host tool) provides the bitstream.
  • SDM Flash: A flash device connected on SDM side provides the bitstream.

The following flash device types can be connected to SDM:

Table 109.   Flash Type Support Status

Flash Type

Support Status

QSPI

Currently supported in the Intel® Quartus® Prime Pro Edition 20.1 release

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