AN 886: Intel® Agilex™ Device Design Guidelines

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Date 8/26/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel® Agilex™ Device Design Guidelines 2. System Specification 3. Device Selection 4. Security Considerations 5. Design Entry 6. Board and Software Considerations 7. Design Implementation, Analysis, Optimization, and Verification 8. Debugging 9. Embedded Software Design Guidelines for Intel® Agilex™ SoC FPGAs
1. Introduction to the Intel® Agilex™ Device Design Guidelines x
1.1. Design Flow 1.2. Introduction to the Intel® Agilex™ Device Design Guidelines Revision History
2. System Specification x
2.1. Design Specifications 2.2. Install Intel® Quartus® Prime Software 2.3. IP Selection 2.4. Simulation 2.5. Preparing for Design Entry 2.6. I/O Summary 2.7. Using Intel® Agilex™ HPS in your Device 2.8. System Specification Revision History
2.3. IP Selection x
2.3.1. Evaluate Available HPS IP 2.3.2. Select Soft IP and I/O Interfaces
2.3.2. Select Soft IP and I/O Interfaces x
2.3.2.1. IP Cores
2.5. Preparing for Design Entry x
2.5.1. Coding Styles and Design Recommendations 2.5.2. Platform Designer
3. Device Selection x
3.1. Device Variant 3.2. PLLs and Clock Routing 3.3. Logic, Memory, and Multiplier Density 3.4. I/O Pin Count, LVDS SERDES Channels, and Package Offering 3.5. Speed Grade 3.6. Vertical Device Migration 3.7. Device Selection Revision History
4. Security Considerations x
4.1. Security Considerations Revision History
5. Design Entry x
5.1. Design Entry for SoC Devices 5.2. Design Entry for FPGA-only Devices 5.3. EMIF Considerations 5.4. Nios® II 5.5. Transceiver Planning 5.6. Reconfiguration 5.7. Design Entry Revision History
5.1. Design Entry for SoC Devices x
5.1.1. Firewall Planning 5.1.2. Boot And Configuration Considerations 5.1.3. HPS Clocking and Reset Design Considerations 5.1.4. Reset Configuration 5.1.5. HPS Pin Multiplexing Design Considerations 5.1.6. HPS I/O Settings: Constraints and Drive Strengths 5.1.7. Design Guidelines for HPS Interfaces 5.1.8. Interfacing between the FPGA and HPS 5.1.9. Implementing the Intel® Agilex™ HPS Component
5.1.2. Boot And Configuration Considerations x
5.1.2.1. Selecting HPS Boot Options 5.1.2.2. Configuration Sources 5.1.2.3. Remote System Update (RSU)
5.1.3. HPS Clocking and Reset Design Considerations x
5.1.3.1. HPS Clock Planning 5.1.3.2. Early Pin Planning and I/O Assignment Analysis 5.1.3.3. Pin Features and Connections for HPS Clocks, Reset and PoR 5.1.3.4. Direct to Factory Pin Support for Remote System Update (RSU) Feature 5.1.3.5. Internal Clocks 5.1.3.6. HPS Peripheral Reset Management
5.1.4. Reset Configuration x
5.1.4.1. HPS Peripheral Reset Management 5.1.4.2. System Reset Considerations
5.1.7. Design Guidelines for HPS Interfaces x
5.1.7.1. Design Considerations for Selecting PHY Interfaces 5.1.7.2. USB Interface Design Guidelines 5.1.7.3. SD/MMC and eMMC Card Interface Design Guidelines 5.1.7.4. Design Guidelines for Flash Interfaces 5.1.7.5. UART Interface Design Guidelines 5.1.7.6. I2C Interface Design Guidelines
5.1.7.1. Design Considerations for Selecting PHY Interfaces x
5.1.7.1.1. HPS EMAC PHY Interfaces 5.1.7.1.2. RMII and RGMII PHY Interfaces 5.1.7.1.3. PHY Interfaces Connected Through FPGA I/O 5.1.7.1.4. Consider Device Driver Availability 5.1.7.1.5. MDIO 5.1.7.1.6. Signal Integrity
5.1.7.4. Design Guidelines for Flash Interfaces x
5.1.7.4.1. NAND Flash Interface Design Guidelines
5.1.8. Interfacing between the FPGA and HPS x
5.1.8.1. Overview of HPS Memory-Mapped Interfaces 5.1.8.2. Recommended System Topologies 5.1.8.3. Recommended Starting Point for HPS-to-FPGA Interface Designs 5.1.8.4. Information on How to Configure and Use the Bridges
5.1.8.1. Overview of HPS Memory-Mapped Interfaces x
5.1.8.1.1. HPS-to-FPGA Bridge 5.1.8.1.2. Lightweight HPS-to-FPGA Bridge 5.1.8.1.3. FPGA-to-HPS Bridge 5.1.8.1.4. Interface Bandwidths
5.1.8.2. Recommended System Topologies x
5.1.8.2.1. System Level Cache Coherency 5.1.8.2.2. HPS Accesses to FPGA Fabric 5.1.8.2.3. MPU Sharing Data with FPGA 5.1.8.2.4. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA Example 1: FPGA Reading Non-Cache Coherent Data from HPS EMIF Directly Example 2: FPGA Writing Non-Cache Coherent Data into HPS EMIF Directly Example 3: FPGA Reading Cache Coherent Data from HPS GUIDELINE: Perform full accesses targeting FPGA-to-HPS bridge. GUIDELINE: Perform cacheable accesses aligned to 64 bytes targeting the FPGA-to-HPS bridge. GUIDELINE: Access 64 bytes per cacheable transaction. Example 4: FPGA Writing Cache Coherent Data to HPS GUIDELINE: When L2 ECC is enabled, ensure that cacheable accesses to the FPGA-to-HPS bridge are aligned to 8-byte boundaries. GUIDELINE: When L2 ECC is enabled, ensure that cacheable accesses to the FPGA-to-HPS bridge have groups of eight write strobes enabled.
5.2. Design Entry for FPGA-only Devices x
5.2.1. Clocking and Reset Design Considerations 5.2.2. I/O and Clock Planning
5.2.2. I/O and Clock Planning x
5.2.2.1. Making FPGA Pin Assignments 5.2.2.2. Early Pin Planning and I/O Assignment Analysis for the FPGA Device 5.2.2.3. I/O Features and Pin Connections 5.2.2.4. Clock and PLL Selection 5.2.2.5. PLL Feature Guidelines 5.2.2.6. Clock Control Features 5.2.2.7. I/O Simultaneous Switching Noise
5.2.2.3. I/O Features and Pin Connections x
5.2.2.3.1. I/O Signaling Type 5.2.2.3.2. Selectable Standards and Flexible I/O Banks 5.2.2.3.3. Dual-Purpose and Special Pin Connections 5.2.2.3.4. Intel® Agilex™ I/O Features
5.2.2.5. PLL Feature Guidelines x
5.2.2.5.1. Clock Feedback Mode 5.2.2.5.2. Clock Outputs
5.3. EMIF Considerations x
5.3.1. Memory Interfaces 5.3.2. HPS EMIF Design Considerations 5.3.3. FPGA EMIF Design Considerations
5.3.2. HPS EMIF Design Considerations x
5.3.2.1. Considerations for Connecting HPS to SDRAM 5.3.2.2. HPS EMIF I/O Locations 5.3.2.3. HPS Memory Debug
6. Board and Software Considerations x
6.1. Early System and Board Planning 6.2. Board Design Guidelines for Intel® Agilex™ SoC FPGAs 6.3. Pin Connection Considerations for Board Design 6.4. Board Considerations Revision History
6.1. Early System and Board Planning x
6.1.1. SmartVID 6.1.2. Intel® FPGA Power and Thermal Calculator 6.1.3. Thermal Management and Design 6.1.4. Temperature Sensing for Thermal Management 6.1.5. Voltage Sensor 6.1.6. Device Power-Up 6.1.7. Power Pin Connections and Power Supplies 6.1.8. Planning for Device Configuration
6.1.7. Power Pin Connections and Power Supplies x
6.1.7.1. Decoupling Capacitors 6.1.7.2. PLL Board Design Guidelines 6.1.7.3. Transceiver Board Design Guidelines
6.1.8. Planning for Device Configuration x
6.1.8.1. Device Power Cycling and Reconfiguration 6.1.8.2. Configuration Scheme Selection 6.1.8.3. Configuration Features 6.1.8.4. Intel® Quartus® Prime Configuration Settings 6.1.8.5. Configuration Pin Connections
6.1.8.2. Configuration Scheme Selection x
6.1.8.2.1. Serial Configuration Devices 6.1.8.2.2. Download Cables
6.1.8.4. Intel® Quartus® Prime Configuration Settings x
6.1.8.4.1. Optional Configuration Pins 6.1.8.4.2. Dual Purpose Configuration Pins
6.1.8.5. Configuration Pin Connections x
6.1.8.5.1. Configuration Pin Voltage Level 6.1.8.5.2. Clock Trace Signal Integrity 6.1.8.5.3. JTAG Pins 6.1.8.5.4. MSEL Configuration Mode Pins 6.1.8.5.5. Other Configuration Pins
6.2. Board Design Guidelines for Intel® Agilex™ SoC FPGAs x
6.2.1. Boundary Scan for HPS 6.2.2. Embedded Software Debugging and Trace
6.3. Pin Connection Considerations for Board Design x
6.3.1. Board-Related Intel® Quartus® Prime Settings 6.3.2. Signal Integrity Considerations 6.3.3. Board-Level Simulation and Advanced I/O Timing Analysis
6.3.1. Board-Related Intel® Quartus® Prime Settings x
6.3.1.1. Unused Pins
6.3.2. Signal Integrity Considerations x
6.3.2.1. High-Speed Board Design 6.3.2.2. Voltage Reference Pins 6.3.2.3. Simultaneous Switching Noise 6.3.2.4. I/O Termination
7. Design Implementation, Analysis, Optimization, and Verification x
7.1. Selecting a Synthesis Tool 7.2. Device Resource Utilization Reports 7.3. Intel® Quartus® Prime Messages 7.4. Timing Constraints and Analysis 7.5. Area and Timing Optimization 7.6. Preserving Performance and Reducing Compilation Time 7.7. Designing with Intel® Hyperflex™ 7.8. Simulation 7.9. Power Analysis 7.10. Power Optimization 7.11. Design Implementation, Analysis, Optimization, and Verification Revision History
7.4. Timing Constraints and Analysis x
7.4.1. Recommended Timing Optimization and Analysis Assignments
7.10. Power Optimization x
7.10.1. Device and Design Power Optimization Techniques 7.10.2. Intel® Quartus® Prime Power Optimization Techniques
7.10.1. Device and Design Power Optimization Techniques x
7.10.1.1. Device Speed Grade 7.10.1.2. Clock Power Management 7.10.1.3. Memory Power Reduction 7.10.1.4. I/O Power Guidelines
7.10.2. Intel® Quartus® Prime Power Optimization Techniques x
7.10.2.1. Power Optimization Advisor
8. Debugging x
8.1. On-Chip Debug Overview 8.2. On-Chip Debugging Tools 8.3. Debugging Revision History
8.1. On-Chip Debug Overview x
8.1.1. Planning Guidelines for Debugging Tools
9. Embedded Software Design Guidelines for Intel® Agilex™ SoC FPGAs x
9.1. Overview 9.2. Golden Hardware Reference Design (GHRD) 9.3. Define Software Requirements 9.4. Define Software Architecture 9.5. Selecting Software Tools 9.6. Choosing the Bootloader Software 9.7. Selecting an Operating System for Your Application 9.8. Assembling Your Software Development Platform for Linux* 9.9. Assembling your Software Development Platform for Partner OS or RTOS 9.10. Driver Considerations 9.11. Boot And Configuration Considerations 9.12. System Reset Considerations 9.13. Flash Considerations 9.14. Develop Application 9.15. Test and Validate 9.16. Embedded Software Design Guidelines Revision History
9.5. Selecting Software Tools x
9.5.1. Selecting Software Build Tools 9.5.2. Selecting Software Debug Tools 9.5.3. Selecting Software Trace Tools
9.7. Selecting an Operating System for Your Application x
9.7.1. Using Linux* or RTOS 9.7.2. Using the Bootloader as a Bare-Metal Framework 9.7.3. Using Symmetrical vs. Asymmetrical Multiprocessing (SMP vs. AMP) Modes
9.8. Assembling Your Software Development Platform for Linux* x
9.8.1. Golden System Reference Design (GSRD) for Linux* 9.8.2. Source Code Management Considerations
9.11. Boot And Configuration Considerations x
9.11.1. Configuration Sources 9.11.2. Configuration Flash 9.11.3. Configuration Clock 9.11.4. Selecting HPS Boot Options 9.11.5. HPS Boot Sources 9.11.6. Remote System Update (RSU)
9.13. Flash Considerations x
9.13.1. Flash Programming Method 9.13.2. Using a Single flash for Both FPGA Configuration and HPS Mass Storage
1. Introduction to the Intel® Agilex™ Device Design Guidelines
2. System Specification
3. Device Selection
4. Security Considerations
5. Design Entry
6. Board and Software Considerations
7. Design Implementation, Analysis, Optimization, and Verification
8. Debugging
9. Embedded Software Design Guidelines for Intel® Agilex™ SoC FPGAs

5.1.8.2.4. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA

Example 1: FPGA Reading Non-Cache Coherent Data from HPS EMIF Directly

In this example the FPGA requires access to data that is stored in the HPS EMIF. For the FPGA to access the same copy of the data as the MPU has access to, the L1 data cache and L2 cache need to be flushed if they already have a copy of the data. Once the HPS EMIF contains the most up-to-date copy of the data, the optimal path for the FPGA to access this data is for FPGA masters to read the data through the FPGA-to-HPS bridge directly targeting the SDRAM.

Figure 9. FPGA Reading Non-Cache Coherent Data

The FPGA-to-HPS bridge can be optimized to maximize the read throughput by setting the bridge width according to your system requirements. Intel recommends to use a burst capable master in the FPGA to read from the SDRAM, capable of posting burst lengths of four beats or larger.

Example 2: FPGA Writing Non-Cache Coherent Data into HPS EMIF Directly

In this example the HPS MPU requires access to data that originates from within the FPGA. For the MPU to be able to access the data coherently after it is written, software may need to flush or invalidate cache lines before the transfer starts, to ensure that the SDRAM contains the latest data after it is written. Failing to perform cache operations can cause one or more cache lines to eventually become evicted overwriting the data that was written by the FPGA master.

Figure 10. FPGA Writing Non-Cache Coherent Data
Note: Like in "Example 1: FPGA Reading Data from HPS EMIF Directly", the FPGA-to-HPS bridge can be optimized to maximize the write throughput by setting the bridge width according to your system requirements.

Example 3: FPGA Reading Cache Coherent Data from HPS

In this example the FPGA requires access to data originating in the HPS. The MPU in the HPS recently accessed this data so there is a chance that the data is still contained in the cache and therefore it may be optimal for the FPGA to access the cached data. To avoid the overhead of software having to flush dirty cache lines the FPGA can perform cache coherent reads through the FPGA-to-HPS bridge. It is important that the buffers being read be relatively small. Otherwise, the L2 cache might thrash reading data from SDRAM for most of the transfer. For large buffer transfers it is more appropriate to have the FPGA read data through the FPGA-to-HPS bridge directly accessing the SDRAM, as shown in "Example 1: FPGA Reading Data from HPS EMIF Directly".

GUIDELINE: Perform full accesses targeting FPGA-to-HPS bridge.

For the transaction to be cacheable, the FPGA master must read from the FPGA-to-HPS bridge and utilize the cache extension signaling of the ACE-Lite protocol. For more information about the ACE-Lite protocol signaling extensions for cache coherent accesses, refer to the Cache Coherency Unit section in the Intel® Agilex™ Hard Processor System Technical Reference Manual.

Figure 11. FPGA Reading Cache Coherent Data

GUIDELINE: Perform cacheable accesses aligned to 64 bytes targeting the FPGA-to-HPS bridge.

The CCU of the HPS is optimized for transactions that are the same size as the cache line (64 bytes). As a result you should attempt to align the data to 64 byte boundaries and ensure after data width adaptation the burst length into the 512-bit FPGA-to-HPS bridge is maximized. For example, a 128-bit FPGA master should align the data to be 64 byte aligned and perform full 128-bit (16-byte) accesses with a burst length of 4.

GUIDELINE: Access 64 bytes per cacheable transaction.

Ensure that each burst transaction accesses 64 bytes. Each transaction must start on a 64-byte boundary.

Table 27.  Burst Lengths for 64-byte Alignment
FPGA Master Width (Bits) Access Size (Bytes) Burst Length
32 4 16
64 8 8
128 16 4
256 32 2
512 64 1

Example 4: FPGA Writing Cache Coherent Data to HPS

In this example the HPS MPU requires access to data that originates in the FPGA. The most efficient mechanism for sharing small blocks of data with the MPU is to have logic in the FPGA perform cacheable writes to the HPS. It is important that the amount of data to be written to the HPS be in the form of relatively small blocks because large block writes cause the L2 cache to thrash, causing the cache to write to SDRAM for most of the transfer. For large buffer transfers it is more appropriate to have the FPGA write data to the FPGA-to-HPS bridge targeting SDRAM directly as shown in Example 2.

GUIDELINE: Perform full accesses targeting FPGA-to-HPS bridge.

For the transaction to be cacheable, the FPGA master must write to the FPGA-to-HPS bridge and utilize the cache extension signaling of the ACE-Lite protocol. For more information about the ACE-Lite protocol signaling extensions for cache coherent accesses, refer to the Cache Coherency Unit section in the Intel® Agilex™ Hard Processor System Technical Reference Manual.

Figure 12. FPGA Writing Cache Coherent DataFor abbreviations, refer to the figure in Overview of HPS Memory-Mapped Interfaces.

GUIDELINE: When L2 ECC is enabled, ensure that cacheable accesses to the FPGA-to-HPS bridge are aligned to 8-byte boundaries.

If you enable error checking and correction (ECC) in the L2 cache you must also ensure each 8-byte group of data is completely written. The L2 cache performs ECC operations on 64-bit boundaries so when performing cacheable accesses you must always align the access to 8-byte boundaries and write to all eight lanes at once. Failing to follow these rules results in double bit errors, which cannot be recovered.

Regardless whether ECC is enabled or disabled, 64 byte cache transactions result in the best performance. For more information about 64 byte cache transactions, refer to GUIDELINE: Access 64 bytes per cacheable transaction in the "Example 3: FPGA Reading Cache Coherent Data from HPS" section.

GUIDELINE: When L2 ECC is enabled, ensure that cacheable accesses to the FPGA-to-HPS bridge have groups of eight write strobes enabled.

  • For FPGA-to-HPS accesses from 32-bit FPGA masters, burst length must be 2, 4, 8, or 16 with all write byte strobes enabled.
  • For FPGA-to-HPS accesses from 64-bit FPGA masters, all write byte strobes must be enabled.
  • For FPGA-to-HPS accesses from 128-bit FPGA masters, the upper eight or lower eight (or both) write byte strobes must be enabled.
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