AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

5.2.2.3.4. Intel® Agilex™ I/O Features

Table 33.   Intel® Agilex™ I/O Features Checklist
Number Done? Checklist Item
1   Check available device I/O features that can help I/O interfaces: slew rate, I/O delays, open-drain, bus hold, programmable pull-up resistors, PCI* clamping diodes, programmable pre-emphasis, and VOD.
2   Consider on-chip termination (OCT) features to save board space.
3   Verify that the required termination scheme is supported for all pin locations.
4   Choose the appropriate mode of DPA, non-DPA, or soft-CDR for high-speed LVDS SERDES interfaces.

For more information, refer to the Intel® Agilex™ LVDS SERDES Design Guidelines section in the Intel® Agilex™ General Purpose I/O and LVDS SERDES User Guide.

The Intel® Agilex™ bi-directional I/O element (IOE) features support rapid system integration while simultaneously providing the high bandwidth required to maximize internal logic capabilities and system-level performance. Advanced features for device interfaces assist in high-speed data transfer into and out of the device and reduce the complexity and cost of the PCB.

Intel recommends performing an IBIS or SPICE simulations to optimize your design settings.

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