AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

6.1.8.5.1. Configuration Pin Voltage Level

Table 70.  Configuration Pin Voltage Level Checklist
Number Done? Checklist Item
1   Ensure VCCIO_SDM and VCCIO of the configuration pins match the voltage level of the external devices used for configuration.

Configuration pins from the Intel® Agilex™ device connect to external devices, for example the Quad SPI flash configuration device, Avalon® -ST host, or SD/MMC flash memories. The voltage level of the configuration pins need to match the voltage level of the devices connected to them. The JTAG and SDM I/Os used as configuration pins are powered by the VCCIO_SDM supply. For Avalon® -ST ×32 and ×16 configuration schemes, the AVST_CLK, AVST_READY, AVST_VALID, and AVST_DATA pins are powered by the VCCIO of the I/O bank in which the pins reside in.

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