AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

2.6. I/O Summary

One of the most important considerations when configuring the device is to understand how the I/O is organized in the Intel® Agilex™ SoC devices.

1. HPS EMIF I/O

There are three modular I/O sub-bank that can connect to SDRAM memory. One of the I/O banks is used to connect the address, command and ECC data signals. The other two banks are for connecting the data signals.

2. HPS Dedicated I/O

These 48 I/O are physically located inside the HPS, are dedicated for the HPS, and are used for the HPS clock and peripherals, including mass storage flash memory.

Note: HPS EMIF I/O and HPS Dedicated I/O are only located on an HPS device.

3. Secure Device Manager (SDM) Dedicated I/O

The SDM has 24 dedicated I/Os, which include JTAG, clock, reset, configuration, reference voltages, boot and configuration flash interfaces, and MSEL.

Note: SDM Dedicated I/O can be found on both FPGA and HPS devices.

4. General Purpose I/O

You can use general purpose I/O for FPGA logic, FPGA external memory interfaces and high-speed serial interfaces. It is possible to export most HPS peripheral interfaces to the FPGA fabric for custom adaptation and routing to FPGA I/O.

Note: GPIO can be found on both FPGA and HPS devices.
The table below summarizes the characteristics of each I/O type.
Table 10.  Summary of I/O Types
  Dedicated HPS I/O HPS EMIF I/O Dedicated SDM I/O General Purpose I/O
Number of Available I/O 48 Up to 3 I/O 48 sub-banks (using 2 I/O96 banks) 24 All other device I/O
Location

Inside the HPS

Only available for devices with HPS.

Only available for devices with HPS.

  • Bottom sub-bank in bank 3C
  • Top and Bottom sub-bank in Bank 3D

Inside the SDM

I/O Columns are in the FPGA device
Voltages Supported 1.8V 1.5V True Differential Signal support of DDR4 protocols 1.8V 1.2V I/O, 1.5V I/O, and high speed serial transceivers
Purpose

HPS Clock, HPS peripherals, mass storage flash, HPS JTAG

HPS main memory FPGA JTAG through SDM dedicated pins, clock, reset, configuration, reference voltages, boot and configuration flash interfaces General purpose and transceiver I/O
Timing Constraints Fixed Provided by memory controller IP Fixed User defined
Recommended Peripherals

HPS peripheral I/O such as Ethernet PHY, USB PHY, mass storage flash (NAND, SD/MMC), TRACE debug.

DDR4 Boot and configuration source, FPGA JTAG through SDM dedicated pins, MSEL signals, and AVSTx8 are connected to the SDM.

Slow speed HPS peripherals (I2C, SPI, EMAC-MII), FPGA I/O such as FPGA EMIFs, transceiver I/O, AVSTx16, AVSTx32, and other parallel and control/status I/O.

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