3.4. I/O Pin Count, LVDS SERDES Channels, and Package Offering
|1||Estimate the number of I/O pins that you require.|
|2||Consider the I/O pins you need to reserve for debugging.|
|3||Verify that the number of LVDS SERDES channels are enough.|
|4||Evaluate fabric speed grade and the transceiver speed grade.|
|5||Consider I/O voltages required for chip to chip interfaces and ensure that they are compatible with supported standards.|
Determine the required number of I/O pins for your application, considering the design’s interface requirements with other system blocks.
Larger densities and package pin counts offer more unidirectional LVDS SERDES channels for differential signaling; ensure that your device density-package combination includes enough LVDS SERDES channels. Other factors can also affect the number of I/O pins required for a design, including simultaneous switching noise (SSN) concerns, pin placement guidelines, pins used as dedicated inputs, I/O standard availability for each I/O bank, differences between I/O standards and speed for row and column I/O banks, and package migration options.
You can compile any existing designs in the Intel® Quartus® Prime software to determine how many I/O pins are used. Also consider reserving I/O pins for debugging.