AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

5.2.2.3.1. I/O Signaling Type

Table 30.  I/O Signaling Type Checklist
Number Done? Checklist Item
1   Plan the I/O signaling type based on the system requirements.
2   Allow the software to assign locations for the negative pin in differential pin pairs.

Intel® Agilex™ devices support a wide range of industry I/O standards, including single-ended, voltage-referenced single-ended, and differential I/O standards. Follow these general guidelines when you select a signaling type.

Single-ended I/O signaling provides a simple rail-to-rail interface. Its speed is limited by the large voltage swing and noise. Single-ended I/Os do not require termination, unless reflection in the system causes undesirable effects.

Voltage-referenced signaling reduces the effects of simultaneous switching outputs (SSO) from pins changing voltage levels at the same time (for example, external memory interface data and address buses). Voltage-referenced signaling also provides an improved logic transition rate with a reduced voltage swing, and minimizes noise caused by reflection with a termination requirement. However, additional termination components are required for the reference voltage source (VTT).

Differential signaling eliminates the interface performance barrier of single-ended and voltage-referenced signaling, with superior speed using an additional inverted closely-coupled data pair. Differential signaling also avoids the requirement for a clean reference voltage. This is possible because of a lower swing voltage and noise immunity with a common mode noise rejection capability. Considerations for this implementation include the requirements for a dedicated PLL to generate a sampling clock, and matched trace lengths to eliminate the phase difference between an inverted and non-inverted pair.

Intel® Agilex™ I/O pins are organized in pairs to support differential standards. Each I/O pin pair can support unidirectional differential input or output operations. Half of the true differential channels support dedicated transmitter pins and the other half support dedicated true receiver pins. In your design source code, define just one pin to represent a differential pair, and make a pin assignment for this positive end of the pair. When you specify a differential I/O standard, the Intel® Quartus® Prime software automatically places the corresponding negative pin.

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