AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

5.1.7.6. I2C Interface Design Guidelines

GUIDELINE: Instantiate the open-drain buffer when routing I2C signals through the FPGA fabric.

When routing I2C signals through the FPGA, note that the I2C pins from the HPS to the FPGA fabric (i2c*_out_data, i2c*_out_clk) are not open-drain and are logic level inverted. Thus, to drive a logic level zero onto the I2C bus, drive the corresponding pin high. This implementation is useful as they can be used to tie to an output enable of a tri-state buffer directly. You must use the altiobuff to implement the open-drain buffer.

Intel recommends that you use I/O Buffer (ALTIOBUF) IP core when you expose I2C to FPGA fabric.

GUIDELINE: Ensure that the pull-ups are added to the external SDA and SCL signals in the board design.

Because the I2C signals are open drain, pull-ups are required to make sure that the bus is pulled high when no device on the bus is pulling it low.

Figure 6. I2C Wiring to FPGA pins

GUIDELINE: Ensure that the high and low clock counts are configured correctly for the speed of the I2C interface

There is an I2C internal clock located in the:
  • SDM—125 MHz
  • HPS—100 MHz
The default settings for the high and low clock counts are configured for 125 MHz, so the default high and low clocks for the HPS I2C are longer than expected.

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