5.3.3. FPGA EMIF Design Considerations
|1||Use the External Memory Interfaces Intel® Agilex™ FPGA IP core for each memory interface, and follow connection guidelines and restrictions in the appropriate documentation.|
|2||For a given sub-bank, most memory pins are tied to a dedicated location. Refer to Intel® Agilex™ External Memory Interface Pin Information to determine available pin usage for EMIF interfaces and the Intel® Agilex™ Device Family Pin Connection Guidelines for pin assignments.|
|3||Generate the External Memory Interfaces Intel Calibration IP and connect it to all the EMIF interfaces located in the same I/O row.|
Intel® Agilex™ devices provide an efficient architecture to quickly and easily fit wide external memory interfaces with their small modular I/O banks. The Intel® Agilex™ FPGA can support DDR external memory on any I/O banks located on the top or bottom I/O row. A memory interface can occupy one or more sub-banks. When multiple sub-banks are needed, the sub-banks must be consecutive.
The data strobe DQS and data DQ pin locations are fixed in Intel® Agilex™ devices. Before you design your device pin-out, refer to the memory interface guidelines for details and important restrictions related to the connections for these and other memory-related signals.
Address and command pins within the address/command bank must follow a fixed pin-out scheme, as defined in the <variation_name>_readme.txt file generated with your IP core. The pin-out scheme varies according to the topology of the memory interface. The pin-out scheme is a hardware requirement that you must follow. Some schemes require three lanes to implement address and command pins, while others require four lanes.
The self-calibrating External Memory Interfaces IP core is optimized to take advantage of the Intel® Agilex™ I/O structure. The External Memory Interfaces IP core allows you to set external memory interface features and helps set up the physical interface (PHY) best suited for your system. If you design multiple memory interfaces into the device using Intel FPGA IP core, generate a unique interface for each instance to ensure good results instead of designing it once and instantiating it multiple times.
In Intel® Agilex™ devices, the calibration IP is instantiated separately from the EMIF IP core. Every EMIF IP core needs to be connected to the calibration IP. You can only have one calibration IP in an I/O row. If you have multiple EMIF IP core located in the same I/O row, connect all the interfaces in the row to the same calibration IP.The following checklist supplements the restrictions found in the EMIF user guide.
|1||All the 96 pins in a given bank (2 sub-banks) share the same voltage level.|
|2||Unused pins in I/O lane of used data bank or address/command bank of EMIF interface are not permitted as GPIO signals.|
|3||Arbitrary placement of data mask pins within data lanes is not permitted. Pin index 6 must be used as data mask pin if DM/RDI/WDBI is enabled.|
|4||True LVDS input clock for PLL reference clock is no longer supported. Intel® recommends that every external memory interface to have its own PLL reference clock source. For more information about clock and voltage, refer to the Intel® Agilex™ Device Data Sheet.|
|5||Every EMIF interface must have its own RZQ pin and must be placed in Lane 2, pin index 2 in the address/command tiles|
|1||Perform board simulation to confirm adequate margin on address/command and data path.|
|2||If you are using DIMM, connect every signal from the FPGA to the DIMM if the design does not use it (for example: wider address width, all CS/CKE/ODT signals)|
|3||Have probe points for voltage rails, address/command channel signals and one data lane.|
|4||Use a programmable reference clock generator for EMIF to support multiple operating frequency|
|5||Leave adequate clearance for socket/cooling solution, and logic analyzer interfaces on the DIMM.|
The guidelines above ensure the board is designed with adequate margin and allow easy probing of critical signals and stability of voltage rails during debug. Ability to change the reference clock generator allows you to test the interface for multiple operating frequency. If the interface works at a lower speed, the interface is correctly pinned out and functional.