AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022

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Document Table of Contents HPS EMAC PHY Interfaces

There are three EMACs based on the Synopsys* DesignWare* 3504‑0 Universal 10/100/1000 Ethernet MAC IP version. When configuring an HPS component for EMAC peripherals within Platform Designer, you must select from one of the following supported PHY interfaces, located in the HPS Dedicated I/O Bank2, for each EMAC instance:
  • Reduced Media Independent Interface (RMII)
  • Reduced Gigabit Media Independent Interface (RGMII)

GUIDELINE: When selecting a PHY device, consider the desired Ethernet rate, available I/O and available transceivers, PHY devices that offer the skew control feature, and device driver availability.

It is possible to adapt the MII/GMII PHY interfaces exposed to the FPGA fabric by the HPS component to other PHY interface standards such as RMII, SGMII, SMII and TBI using soft adaptation logic in the FPGA and features in the general-purpose FPGA I/O and transceiver FPGA I/O.

For more information, refer to the device drivers available for your operating system of choice or the Linux device driver provided with the Intel® Agilex™ Transceiver-SoC Development Kit.

The EMAC provides a variety of PHY interfaces and control options through the HPS and the FPGA I/Os.

Note: You can connect PHYs to the HPS EMACs through the FPGA fabric using the GMII and MII bus interfaces for Gigabit and 10/100 Mbps access respectively. You can refer to the Intel® Stratix® 10 SoC SGMII Reference Design on to learn how to implement this type of design. For more information about Embedded Peripheral IPs offered, please refer to the Embedded Peripheral IP User Guide.

Determine Ethernet Rate

For information about allowable Ethernet rates, refer to the following documents:
  • Intel® Agilex™ Hard Processor System Technical Reference Manual
  • Intel® Agilex™ FPGA Data Sheet
2 The HPS Dedicated I/O Bank consists of 48 I/O with 1.8V signaling.