AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

5.2.2.3.2. Selectable Standards and Flexible I/O Banks

Table 31.  Selectable Standards and Flexible I/O Banks Checklist
Number Done? Checklist Item
1   Select a suitable signaling type and I/O standard for each I/O pin. The I/O banks are located in the top and bottom I/O bank row. Each I/O bank contains its own PLL, DPA, and SERDES circuitries.
2   Ensure that the appropriate I/O standard support is supported in the targeted I/O bank.
3   Place I/O pins that share voltage levels in the same I/O bank.
4   Verify that all output signals in each I/O bank are intended to drive out at the bank’s VCCIO voltage level.
5   Verify that all voltage-referenced signals in each I/O bank are intended to use the bank’s VREF voltage level.
6   Check the I/O bank support for LVDS and transceiver features.
7   Place I/O pins that share OCT calibration block in the same I/O tile.

Intel® Agilex™ I/O pins are arranged in groups called modular I/O banks. Be sure to use the correct dedicated pin inputs for signals such as clocks and global control signals.

The board must supply each bank with one VCCIO_PIO voltage level for every VCCIO_PIO pin in a bank. Each I/O bank is powered by the VCCIO_PIO pins of that particular bank, and is independent of the VCCIO_PIO pins of other I/O banks. A single I/O bank supports single-ended or voltage-referenced output and input signals that are driving and receiving at the same voltage as the VCCIO_PIO. An I/O bank can simultaneously support any number of input signals with different I/O standards.

To accommodate voltage-referenced I/O standards, each I/O bank supports multiple VREF pins feeding a common VREF bus. Intel® Agilex™ GPIO bank supports internal and external VREF types. Each I/O lane must share the same VREF type. Set the VREF pins to the correct voltage for the I/O standards in the bank. Each I/O bank can only have a single VCCIO_PIO voltage level and a single VREF voltage level at a given time. If the VREF pins are not used as voltage references, they cannot be used as generic I/O pins and should be tied to VCCIO_PIO of that same bank or GND.

An I/O bank including single-ended or differential standards can support voltage-referenced standards as long as all voltage-referenced standards use the same VREF setting. Voltage-referenced bi-directional and output signals must drive out at the I/O bank’s VCCIO_PIO voltage level.

Different I/O banks include different support for 1.5V True Differential Signaling, and the Intel® Agilex™ transceiver banks include additional I/O support.

The GPIO bank supports true differential input standard at 1.2V/ 1.5V VCCIO_PIO . The true differential output standard is supported at 1.5V VCCIO_PIO bank. The I/O pins form pairs of unidirectional true differential channels.

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