AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

5.1.4.2. System Reset Considerations

Table 22.  System Reset Checklist
Number Done? Checklist Item
1   Intel® strongly recommends using the Reset Release IP in your design to provide a known initialized state for your logic to begin operation. The Reset Release IP is described in the Intel® Agilex™ Configuration User Guide.
After any one of the four Watchdog timers expire and generates a system reset request to the SDM, the SDM then performs one of three types of system resets:
  • HPS Cold reset
  • HPS Warm reset
  • Trigger Remote Update
Note: One of these three options can be chosen from within the Intel® Quartus® Prime Pro Edition tool.
In the Intel® Quartus® Prime Pro Edition tool, you must:
  1. Select the HPS Clocks and resets tab.
  2. Select the Resets tab.
  3. Click on the “Enable watchdog reset” check box.
  4. Choose one of three choices from the pull-down menu for the “How SDM handles HPS watchdog reset” label:
    • HPS Cold reset
      • Impact on HPS—The SDM holds the processor in reset. The SDM loads the FSBL from the same bitstream that was loaded into the device prior to the cold reset into the HPS on-chip memory. When successfully completed, the SDM releases the HPS reset causing the processor to start executing code from the reset exception address.
      • Impact on FPGA—The FPGA core fabric is untouched during the reset. After exiting reset, software determines whether to reconfigure the FPGA portion.
    • HPS Warm reset
      • Impact on HPS—The SDM holds the processor in reset. The FSBL remains in the on-chip RAM during a warm reset. The SDM takes the processor out of reset, and the processor runs the FSBL in on-chip RAM.
      • Impact on FPGA—The FPGA portion is left alone during the reset. After exiting reset, software determines whether to reconfigure the FPGA portion.
    • Trigger Remote Update
      • Impact on HPS—The SDM holds the processor in reset. The SDM loads the FSBL from the next valid *.pof image or factory image into the HPS on-chip memory. The *.pof contains the data to configure the FPGA portion of the SoC and the FSBL payload. When successfully completed, the SDM releases the HPS from reset and the processor begins executing code from the reset exception address.
      • Impact on FPGA—The FPGA portion is first erased, then reconfigured with the next valid Core RBF or Factory Core RBF. There must always be a valid factory RBF present.

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