AN 886: Intel® Agilex™ Device Design Guidelines

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ID 683634
Date 8/26/2022
Public
Document Table of Contents

5.1.8.1.3. FPGA-to-HPS Bridge

GUIDELINE: Use the FPGA-to-HPS bridge for cache coherent memory accesses to the CCU or non-cacheable accesses to the HPS SDRAM from masters in the FPGA.

The FPGA-to-HPS bridge provides access to the peripherals in the HPS or access to the HPS SDRAM from the FPGA. This access is available to any master implemented in the FPGA fabric. You can configure the bridge slave, which is exposed to the FPGA fabric, to support the ACE*-Lite protocol, with a data width of 128, 256, and 512 bits.

For more information about the ACE-Lite protocol extensions for cache coherent transactions, refer to the AMBA* AXI and ACE Protocol Specification on the Arm* Developer website.

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