5.2.1. Clocking and Reset Design Considerations
You must follow the configuration clocking guidelines detailed in the Intel® Agilex™ Configuration User Guide to ensure proper operation. The continual increases in clock frequency, device size, and design complexity now necessitate a well-thought out reset strategy that considers the possible effects of slight differences in the release from reset. This reset strategy must hold the device in reset until all registers and core logic are in user mode. Intel® strongly recommends that you use the nINIT_DONE. The output of the Reset Release Intel® Agilex™ FPGA IP is one of the initial inputs to your reset circuit. For more information, refer to AN 891: Using the Reset Release FPGA IP.