AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

6.1.8.5.2. Clock Trace Signal Integrity

Table 71.  Clock Trace Signal Integrity Checklist
Number Done? Checklist Item
1   Design configuration clock traces to be noise-free.

Board trace for clocks used in configuration, for example TCK, AS_CLK, AVSTx8_CLK, AVST_CLK, SDMMC_CFG_CCLK, and OSC_CLK_1 clock input, should produce clean signals with no overshoot, undershoot, or ringing. When designing the board, lay out the configuration clock traces with the same techniques used to lay out a clock line. Any overshoot, undershoot, ringing, or other noise on the clock signal can cause configuration failure. Make sure to have clock routing as stripline. Keep the clock routing away from any high-speed signals to isolate the clock signals from other signals.

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